mn10300.c (notice_update_cc): Use CC_SET_ZN and CC_SET_ZNV.
* mn10300.c (notice_update_cc): Use CC_SET_ZN and CC_SET_ZNV.
* mn10300.h (CC_NO_CARRY): Define.
* mn10300.md: Use "set_zn" and "set_znv" to more accurately
describe cc0 status.
From-SVN: r14019
This commit is contained in:
Jeff Law
parent
31b663c33a
commit
d116300be8
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@ -596,18 +596,19 @@ notice_update_cc (body, insn)
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cc_status.value1 = 0;
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break;
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case CC_SET_ZN_C0:
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case CC_SET_ZN:
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/* Insn sets the Z,N flags of CC to recog_operand[0].
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V is always set to 0. C may or may not be set to 0 but that's ok
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because alter_cond will change tests to use EQ/NE. */
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V,C are unusable. */
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CC_STATUS_INIT;
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cc_status.flags |= CC_NO_OVERFLOW | CC_OVERFLOW_UNUSABLE;
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cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
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cc_status.value1 = recog_operand[0];
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break;
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case CC_TST:
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/* The insn sets all the condition codes, except v is bogus. */
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case CC_SET_ZNV:
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/* Insn sets the Z,N,V flags of CC to recog_operand[0].
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C is unusable. */
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CC_STATUS_INIT;
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cc_status.flags |= CC_NO_CARRY;
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cc_status.value1 = recog_operand[0];
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break;
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@ -709,6 +709,7 @@ extern struct rtx_def *mn10300_builtin_saveregs ();
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Do not alter them if the instruction would not alter the cc's. */
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#define CC_OVERFLOW_UNUSABLE 0x200
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#define CC_NO_CARRY CC_NO_OVERFLOW
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#define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
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/* Compute the cost of computing a constant rtl expression RTX
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@ -30,14 +30,12 @@
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;; none_0hit - insn does not affect cc but it does modify operand 0
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;; This attribute is used to keep track of when operand 0 changes.
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;; See the description of NOTICE_UPDATE_CC for more info.
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;; set - insn sets flags z,n. v is unusable c is set to 0.
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;; (c may not really be set to 0 but that's ok, we don't need it anyway).
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;; set_zn_c0 - insn sets z,n to usable values. v is unknown. c may or may not
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;; be known (if it isn't that's ok, we don't need it anyway).
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;; set_znv - insn sets z,n,v to useable values; c is unusable.
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;; set_zn - insn sets z,n to useable values; v,c are unuseable.
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;; compare - compare instruction
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;; invert -- like compare, but flags are inverted.
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;; clobber - value of cc is unknown
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(define_attr "cc" "none,none_0hit,tst,set_zn_c0,compare,clobber,invert"
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(define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber,invert"
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(const_string "clobber"))
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;; ----------------------------------------------------------------------
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@ -620,19 +618,19 @@
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[(set (cc0) (match_operand:SI 0 "register_operand" "da"))]
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""
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"* return output_tst (operands[0], insn);"
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[(set_attr "cc" "tst")])
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[(set_attr "cc" "set_znv")])
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(define_insn ""
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[(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "d")))]
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""
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"* return output_tst (operands[0], insn);"
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[(set_attr "cc" "tst")])
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[(set_attr "cc" "set_znv")])
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(define_insn ""
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[(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "d")))]
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""
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"* return output_tst (operands[0], insn);"
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[(set_attr "cc" "tst")])
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[(set_attr "cc" "set_znv")])
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(define_insn "cmpsi"
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@ -681,7 +679,7 @@
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add %2,%0
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add %2,%0
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mov %2,%0\;add %1,%0"
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[(set_attr "cc" "set_zn_c0,none_0hit,none_0hit,set_zn_c0,none_0hit,set_zn_c0")])
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[(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
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(define_expand "adddi3"
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[(set (reg:DI 0) (match_operand:DI 1 "register_operand" ""))
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@ -735,7 +733,7 @@
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(match_operand:SI 2 "nonmemory_operand" "dai")))]
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""
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"sub %2,%0"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_zn")])
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(define_expand "negsi2"
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[(set (match_operand:SI 0 "register_operand" "")
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@ -775,7 +773,7 @@
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(match_operand:SI 2 "register_operand" "d")))]
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""
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"mul %2,%0"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_zn")])
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(define_expand "udivmodsi4"
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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@ -805,7 +803,7 @@
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else
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return \"divu %2,%0\;mov mdr,%3\";
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}"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_zn")])
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(define_expand "divmodsi4"
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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@ -830,7 +828,7 @@
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else
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return \"ext %0\;div %2,%0\;mov mdr,%3\";
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}"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_zn")])
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(define_insn "clear_mdr"
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[(unspec_volatile [(const_int 2)] 0)
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@ -872,7 +870,7 @@
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return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
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return \"and %2,%0\";
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}"
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[(set_attr "cc" "none_0hit,set_zn_c0")])
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[(set_attr "cc" "none_0hit,set_znv")])
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;; ----------------------------------------------------------------------
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;; OR INSTRUCTIONS
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@ -884,7 +882,7 @@
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(match_operand:SI 2 "nonmemory_operand" "di")))]
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""
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"or %2,%0"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_znv")])
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;; ----------------------------------------------------------------------
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;; XOR INSTRUCTIONS
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@ -896,7 +894,7 @@
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(match_operand:SI 2 "nonmemory_operand" "di")))]
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""
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"xor %2,%0"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_znv")])
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;; ----------------------------------------------------------------------
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;; NOT INSTRUCTIONS
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@ -907,7 +905,7 @@
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(not:SI (match_operand:SI 1 "register_operand" "0")))]
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""
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"not %0"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_znv")])
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;; -----------------------------------------------------------------
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;; BIT FIELDS
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@ -944,7 +942,7 @@
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"@
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bclr %N1,%A0
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and %1,%0"
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[(set_attr "cc" "clobber,set_zn_c0")])
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[(set_attr "cc" "clobber,set_znv")])
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(define_insn ""
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[(set (match_operand:QI 0 "general_operand" "=R,d")
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@ -955,7 +953,7 @@
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"@
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bset %1,%A0
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or %1,%0"
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[(set_attr "cc" "clobber")])
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[(set_attr "cc" "clobber,set_znv")])
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(define_insn ""
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[(set (cc0)
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@ -982,7 +980,7 @@
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output_asm_insn (\"btst %1,%0\", xoperands);
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return \"\";
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}"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_znv")])
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(define_insn ""
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[(set (cc0)
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@ -1012,14 +1010,14 @@
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output_asm_insn (\"btst %1,%A0\", xoperands);
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return \"\";
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}"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_znv")])
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(define_insn ""
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[(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "d")
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(match_operand:SI 1 "const_int_operand" "")))]
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""
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"btst %1,%0"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_znv")])
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(define_insn ""
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[(set (cc0)
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@ -1030,7 +1028,7 @@
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"@
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btst %1,%A0
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btst %1,%0"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_znv")])
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;; ----------------------------------------------------------------------
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@ -1326,7 +1324,7 @@
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asl2 %0\;add %0,%0
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asl2 %0\;asl2 %0
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asl %2,%0"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_zn")])
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(define_insn "lshrsi3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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@ -1335,7 +1333,7 @@
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(match_operand:QI 2 "nonmemory_operand" "di")))]
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""
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"lsr %2,%0"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_zn")])
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(define_insn "ashrsi3"
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[(set (match_operand:SI 0 "register_operand" "=d")
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@ -1344,7 +1342,7 @@
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(match_operand:QI 2 "nonmemory_operand" "di")))]
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""
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"asr %2,%0"
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[(set_attr "cc" "set_zn_c0")])
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[(set_attr "cc" "set_zn")])
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;; ----------------------------------------------------------------------
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;; PROLOGUE/EPILOGUE
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