c4x-protos.h (c4x_rpts_cycles, [...]): Delete.
* config/c4x/c4x-protos.h (c4x_rpts_cycles, c4x_cpu_version): Delete. * config/c4x/c4x.h (SMALL_MEMORY_FLAG, MPYI_FLAG, FAST_FIX_FLAG) (RPTS_FLAG, C3X_FLAG, TI_FLAG, PARANOID_FLAG, MEMPARM_FLAG, DEVEL_FLAG) (RPTB_FLAG, BK_FLAG, DB_FLAG, DEBUG_FLAG, HOIST_FLAG) (LOOP_UNSIGNED_FLAG, FORCE_FLAG, PRESERVE_FLOAT_FLAG) (PARALLEL_INSN_FLAG, PARALLEL_MPY_FLAG, ALIASES_FLAG, C30_FLAG) (C31_FLAG, C32_FLAG, C33_FLAG, C40_FLAG, C44_FLAG, TARGET_SWITCHES) (TARGET_DEFAULT, TARGET_SMALL, TARGET_MPYI, TARGET_FAST_FIX) (TARGET_RPTS, TARGET_TI, TARGET_PARANOID, TARGET_MEMPARM, TARGET_DEVEL) (TARGET_RPTB, TARGET_BK, TARGET_DB, TARGET_DEBUG, TARGET_HOIST) (TARGET_LOOP_UNSIGNED, TARGET_FORCE, TARGET_PRESERVE_FLOAT) (TARGET_PARALLEL, TARGET_PARALLEL_MPY, TARGET_ALIASES) (c4x_rpts_cycles_string, c4x_cpu_version_string) (TARGET_OPTIONS): Delete. (c4x_rpts_cycles, c4x_cpu_version): Declare. (TARGET_C3X, TARGET_C30, TARGET_C31, TARGET_C32, TARGET_C33) (TARGET_C40, TARGET_C44): Redefine in terms of c4x_cpu_version. * config/c4x/c4x.c (c4x_rpts_cycles_string): Delete. (c4x_cpu_version_string): Delete. (TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults. (c4x_handle_option): New function. Map -m3x and -m4x options to the equivalent -mcpu= option. (c4x_override_options): Remove -mrpts= and -mcpu= handling from here. Deal with the extra conditions in the old TARGET_MPYI, TARGET_RPTB, TARGET_DB, TARGET_PARALLEL and TARGET_PARALLEL_MPY macros by setting or clearing the appropriate MASK_* bit. (c4x_file_start): Use c4x_cpu_version. * config/c4x/c4x.opt: New file. From-SVN: r97239
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
f9b4c1db7d
commit
d12f3c1f9d
@ -1,3 +1,34 @@
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2005-03-30 Richard Sandiford <rsandifo@redhat.com>
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* config/c4x/c4x-protos.h (c4x_rpts_cycles, c4x_cpu_version): Delete.
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* config/c4x/c4x.h (SMALL_MEMORY_FLAG, MPYI_FLAG, FAST_FIX_FLAG)
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(RPTS_FLAG, C3X_FLAG, TI_FLAG, PARANOID_FLAG, MEMPARM_FLAG, DEVEL_FLAG)
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(RPTB_FLAG, BK_FLAG, DB_FLAG, DEBUG_FLAG, HOIST_FLAG)
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(LOOP_UNSIGNED_FLAG, FORCE_FLAG, PRESERVE_FLOAT_FLAG)
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(PARALLEL_INSN_FLAG, PARALLEL_MPY_FLAG, ALIASES_FLAG, C30_FLAG)
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(C31_FLAG, C32_FLAG, C33_FLAG, C40_FLAG, C44_FLAG, TARGET_SWITCHES)
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(TARGET_DEFAULT, TARGET_SMALL, TARGET_MPYI, TARGET_FAST_FIX)
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(TARGET_RPTS, TARGET_TI, TARGET_PARANOID, TARGET_MEMPARM, TARGET_DEVEL)
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(TARGET_RPTB, TARGET_BK, TARGET_DB, TARGET_DEBUG, TARGET_HOIST)
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(TARGET_LOOP_UNSIGNED, TARGET_FORCE, TARGET_PRESERVE_FLOAT)
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(TARGET_PARALLEL, TARGET_PARALLEL_MPY, TARGET_ALIASES)
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(c4x_rpts_cycles_string, c4x_cpu_version_string)
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(TARGET_OPTIONS): Delete.
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(c4x_rpts_cycles, c4x_cpu_version): Declare.
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(TARGET_C3X, TARGET_C30, TARGET_C31, TARGET_C32, TARGET_C33)
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(TARGET_C40, TARGET_C44): Redefine in terms of c4x_cpu_version.
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* config/c4x/c4x.c (c4x_rpts_cycles_string): Delete.
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(c4x_cpu_version_string): Delete.
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(TARGET_DEFAULT_TARGET_FLAGS, TARGET_HANDLE_OPTION): Override defaults.
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(c4x_handle_option): New function. Map -m3x and -m4x options to the
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equivalent -mcpu= option.
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(c4x_override_options): Remove -mrpts= and -mcpu= handling from here.
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Deal with the extra conditions in the old TARGET_MPYI, TARGET_RPTB,
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TARGET_DB, TARGET_PARALLEL and TARGET_PARALLEL_MPY macros by setting
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or clearing the appropriate MASK_* bit.
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(c4x_file_start): Use c4x_cpu_version.
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* config/c4x/c4x.opt: New file.
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2005-03-30 Richard Sandiford <rsandifo@redhat.com>
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* doc/options.texi: Document the new MaskExists flag.
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@ -274,9 +274,6 @@ extern GTY(()) rtx c4x_compare_op1; /* Operand 1 for comparisons. */
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extern enum reg_class c4x_regclass_map[FIRST_PSEUDO_REGISTER];
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extern enum machine_mode c4x_caller_save_map[FIRST_PSEUDO_REGISTER];
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extern int c4x_rpts_cycles; /* Max cycles for RPTS. */
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extern int c4x_cpu_version; /* Cpu version C30/31/32/40/44. */
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extern void c4x_pr_CODE_SECTION (struct cpp_reader *);
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extern void c4x_pr_DATA_SECTION (struct cpp_reader *);
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extern void c4x_pr_FUNC_IS_PURE (struct cpp_reader *);
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@ -152,9 +152,7 @@ enum machine_mode c4x_caller_save_map[FIRST_PSEUDO_REGISTER] =
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rtx c4x_compare_op0;
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rtx c4x_compare_op1;
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const char *c4x_rpts_cycles_string;
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int c4x_rpts_cycles = 0; /* Max. cycles for RPTS. */
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const char *c4x_cpu_version_string;
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int c4x_cpu_version = 40; /* CPU version C30/31/32/33/40/44. */
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/* Pragma definitions. */
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@ -167,6 +165,7 @@ tree interrupt_tree = NULL_TREE;
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tree naked_tree = NULL_TREE;
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/* Forward declarations */
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static bool c4x_handle_option (size_t, const char *, int);
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static int c4x_isr_reg_used_p (unsigned int);
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static int c4x_leaf_function_p (void);
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static int c4x_naked_function_p (void);
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@ -221,6 +220,13 @@ static tree c4x_gimplify_va_arg_expr (tree, tree, tree *, tree *);
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#undef TARGET_ASM_EXTERNAL_LIBCALL
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#define TARGET_ASM_EXTERNAL_LIBCALL c4x_external_libcall
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/* Play safe, not the fastest code. */
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#undef TARGET_DEFAULT_TARGET_FLAGS
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#define TARGET_DEFAULT_TARGET_FLAGS (MASK_ALIASES | MASK_PARALLEL \
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| MASK_PARALLEL_MPY | MASK_RPTB)
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#undef TARGET_HANDLE_OPTION
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#define TARGET_HANDLE_OPTION c4x_handle_option
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#undef TARGET_ATTRIBUTE_TABLE
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#define TARGET_ATTRIBUTE_TABLE c4x_attribute_table
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@ -258,6 +264,41 @@ static tree c4x_gimplify_va_arg_expr (tree, tree, tree *, tree *);
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struct gcc_target targetm = TARGET_INITIALIZER;
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/* Implement TARGET_HANDLE_OPTION. */
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static bool
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c4x_handle_option (size_t code, const char *arg, int value)
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{
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switch (code)
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{
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case OPT_m30: c4x_cpu_version = 30; return true;
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case OPT_m31: c4x_cpu_version = 31; return true;
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case OPT_m32: c4x_cpu_version = 32; return true;
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case OPT_m33: c4x_cpu_version = 33; return true;
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case OPT_m40: c4x_cpu_version = 40; return true;
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case OPT_m44: c4x_cpu_version = 44; return true;
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case OPT_mcpu_:
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if (arg[0] == 'c' || arg[0] == 'C')
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arg++;
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value = atoi (arg);
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switch (value)
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{
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case 30: case 31: case 32: case 33: case 40: case 44:
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c4x_cpu_version = value;
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return true;
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}
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return false;
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case OPT_mrpts_:
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c4x_rpts_cycles = value;
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return true;
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default:
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return true;
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}
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}
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/* Override command line options.
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Called once after all options have been parsed.
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Mostly we process the processor
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@ -266,59 +307,6 @@ struct gcc_target targetm = TARGET_INITIALIZER;
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void
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c4x_override_options (void)
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{
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if (c4x_rpts_cycles_string)
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c4x_rpts_cycles = atoi (c4x_rpts_cycles_string);
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else
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c4x_rpts_cycles = 0;
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if (TARGET_C30)
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c4x_cpu_version = 30;
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else if (TARGET_C31)
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c4x_cpu_version = 31;
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else if (TARGET_C32)
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c4x_cpu_version = 32;
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else if (TARGET_C33)
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c4x_cpu_version = 33;
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else if (TARGET_C40)
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c4x_cpu_version = 40;
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else if (TARGET_C44)
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c4x_cpu_version = 44;
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else
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c4x_cpu_version = 40;
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/* -mcpu=xx overrides -m40 etc. */
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if (c4x_cpu_version_string)
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{
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const char *p = c4x_cpu_version_string;
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/* Also allow -mcpu=c30 etc. */
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if (*p == 'c' || *p == 'C')
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p++;
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c4x_cpu_version = atoi (p);
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}
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target_flags &= ~(C30_FLAG | C31_FLAG | C32_FLAG | C33_FLAG |
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C40_FLAG | C44_FLAG);
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switch (c4x_cpu_version)
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{
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case 30: target_flags |= C30_FLAG; break;
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case 31: target_flags |= C31_FLAG; break;
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case 32: target_flags |= C32_FLAG; break;
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case 33: target_flags |= C33_FLAG; break;
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case 40: target_flags |= C40_FLAG; break;
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case 44: target_flags |= C44_FLAG; break;
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default:
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warning ("unknown CPU version %d, using 40.\n", c4x_cpu_version);
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c4x_cpu_version = 40;
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target_flags |= C40_FLAG;
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}
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if (TARGET_C30 || TARGET_C31 || TARGET_C32 || TARGET_C33)
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target_flags |= C3X_FLAG;
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else
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target_flags &= ~C3X_FLAG;
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/* Convert foo / 8.0 into foo * 0.125, etc. */
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set_fast_math_flags (1);
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@ -326,6 +314,15 @@ c4x_override_options (void)
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This provides compatibility with the old -mno-aliases option. */
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if (! TARGET_ALIASES && ! flag_argument_noalias)
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flag_argument_noalias = 1;
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if (!TARGET_C3X)
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target_flags |= MASK_MPYI | MASK_DB;
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if (optimize < 2)
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target_flags &= ~(MASK_RPTB | MASK_PARALLEL);
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if (!TARGET_PARALLEL)
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target_flags &= ~MASK_PARALLEL_MPY;
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}
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@ -4409,16 +4406,8 @@ c4x_external_ref (const char *name)
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static void
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c4x_file_start (void)
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{
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int dspversion = 0;
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if (TARGET_C30) dspversion = 30;
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if (TARGET_C31) dspversion = 31;
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if (TARGET_C32) dspversion = 32;
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if (TARGET_C33) dspversion = 33;
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if (TARGET_C40) dspversion = 40;
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if (TARGET_C44) dspversion = 44;
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default_file_start ();
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fprintf (asm_out_file, "\t.version\t%d\n", dspversion);
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fprintf (asm_out_file, "\t.version\t%d\n", c4x_cpu_version);
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fputs ("\n\t.data\ndata_sec:\n", asm_out_file);
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}
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@ -123,186 +123,27 @@
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#define ENDFILE_SPEC ""
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/* Target compilation option flags. */
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#define SMALL_MEMORY_FLAG 0x0000001 /* Small memory model. */
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#define MPYI_FLAG 0x0000002 /* Use 24-bit MPYI for C3x. */
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#define FAST_FIX_FLAG 0x0000004 /* Fast fixing of floats. */
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#define RPTS_FLAG 0x0000008 /* Allow use of RPTS. */
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#define C3X_FLAG 0x0000010 /* Emit C3x code. */
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#define TI_FLAG 0x0000020 /* Be compatible with TI assembler. */
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#define PARANOID_FLAG 0x0000040 /* Be paranoid about DP reg. in ISRs. */
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#define MEMPARM_FLAG 0x0000080 /* Pass arguments on stack. */
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#define DEVEL_FLAG 0x0000100 /* Enable features under development. */
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#define RPTB_FLAG 0x0000200 /* Enable repeat block. */
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#define BK_FLAG 0x0000400 /* Use BK as general register. */
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#define DB_FLAG 0x0000800 /* Use decrement and branch for C3x. */
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#define DEBUG_FLAG 0x0001000 /* Enable debugging of GCC. */
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#define HOIST_FLAG 0x0002000 /* Force constants into registers. */
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#define LOOP_UNSIGNED_FLAG 0x0004000 /* Allow unsigned loop counters. */
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#define FORCE_FLAG 0x0008000 /* Force op0 and op1 to be same. */
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#define PRESERVE_FLOAT_FLAG 0x0010000 /* Save all 40 bits for floats. */
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#define PARALLEL_INSN_FLAG 0x0020000 /* Allow parallel insns. */
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#define PARALLEL_MPY_FLAG 0x0040000 /* Allow MPY||ADD, MPY||SUB insns. */
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#define ALIASES_FLAG 0x0080000 /* Assume mem refs possibly aliased. */
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#define C30_FLAG 0x0100000 /* Emit C30 code. */
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#define C31_FLAG 0x0200000 /* Emit C31 code. */
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#define C32_FLAG 0x0400000 /* Emit C32 code. */
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#define C33_FLAG 0x0800000 /* Emit C33 code. */
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#define C40_FLAG 0x1000000 /* Emit C40 code. */
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#define C44_FLAG 0x2000000 /* Emit C44 code. */
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/* Run-time compilation parameters selecting different hardware subsets.
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Macro to define tables used to set the flags.
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This is a list in braces of triplets in braces,
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each pair being { "NAME", VALUE, "DESCRIPTION" }
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where VALUE is the bits to set or minus the bits to clear.
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An empty string NAME is used to identify the default VALUE. */
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#define TARGET_SWITCHES \
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{ { "small", SMALL_MEMORY_FLAG, \
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N_("Small memory model") }, \
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{ "big", -SMALL_MEMORY_FLAG, \
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N_("Big memory model") }, \
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{ "mpyi", MPYI_FLAG, \
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N_("Use MPYI instruction for C3x") }, \
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{ "no-mpyi", -MPYI_FLAG, \
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N_("Do not use MPYI instruction for C3x") }, \
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{ "fast-fix", FAST_FIX_FLAG, \
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N_("Use fast but approximate float to integer conversion") }, \
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{ "no-fast-fix", -FAST_FIX_FLAG, \
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N_("Use slow but accurate float to integer conversion") }, \
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{ "rpts", RPTS_FLAG, \
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N_("Enable use of RTPS instruction") }, \
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{ "no-rpts", -RPTS_FLAG, \
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N_("Disable use of RTPS instruction") }, \
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{ "rptb", RPTB_FLAG, \
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N_("Enable use of RTPB instruction") }, \
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{ "no-rptb", -RPTB_FLAG, \
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N_("Disable use of RTPB instruction") }, \
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{ "30", C30_FLAG, \
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N_("Generate code for C30 CPU")}, \
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{ "31", C31_FLAG, \
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N_("Generate code for C31 CPU")}, \
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{ "32", C32_FLAG, \
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N_("Generate code for C32 CPU")}, \
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{ "33", C33_FLAG, \
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N_("Generate code for C33 CPU")}, \
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{ "40", C40_FLAG, \
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N_("Generate code for C40 CPU")}, \
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{ "44", C44_FLAG, \
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N_("Generate code for C44 CPU")}, \
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{ "ti", TI_FLAG, \
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N_("Emit code compatible with TI tools")}, \
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{ "no-ti", -TI_FLAG, \
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N_("Emit code to use GAS extensions")}, \
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{ "paranoid", PARANOID_FLAG, \
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N_("Save DP across ISR in small memory model") }, \
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{ "no-paranoid", -PARANOID_FLAG, \
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N_("Don't save DP across ISR in small memory model") }, \
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{ "isr-dp-reload", PARANOID_FLAG, \
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N_("Save DP across ISR in small memory model") }, \
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{ "no-isr-dp-reload", -PARANOID_FLAG, \
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N_("Don't save DP across ISR in small memory model") }, \
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{ "memparm", MEMPARM_FLAG, \
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N_("Pass arguments on the stack") }, \
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{ "regparm", -MEMPARM_FLAG, \
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N_("Pass arguments in registers") }, \
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{ "devel", DEVEL_FLAG, \
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N_("Enable new features under development") }, \
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{ "no-devel", -DEVEL_FLAG, \
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N_("Disable new features under development") }, \
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{ "bk", BK_FLAG, \
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N_("Use the BK register as a general purpose register") }, \
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{ "no-bk", -BK_FLAG, \
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N_("Do not allocate BK register") }, \
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{ "db", DB_FLAG, \
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N_("Enable use of DB instruction") }, \
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{ "no-db", -DB_FLAG, \
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N_("Disable use of DB instruction") }, \
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{ "debug", DEBUG_FLAG, \
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N_("Enable debugging") }, \
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{ "no-debug", -DEBUG_FLAG, \
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N_("Disable debugging") }, \
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{ "hoist", HOIST_FLAG, \
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N_("Force constants into registers to improve hoisting") }, \
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{ "no-hoist", -HOIST_FLAG, \
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N_("Don't force constants into registers") }, \
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{ "force", FORCE_FLAG, \
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N_("Force RTL generation to emit valid 3 operand insns") }, \
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{ "no-force", -FORCE_FLAG, \
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N_("Allow RTL generation to emit invalid 3 operand insns") }, \
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{ "loop-unsigned", LOOP_UNSIGNED_FLAG, \
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N_("Allow unsigned iteration counts for RPTB/DB") }, \
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{ "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
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N_("Disallow unsigned iteration counts for RPTB/DB") }, \
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{ "preserve-float", PRESERVE_FLOAT_FLAG, \
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N_("Preserve all 40 bits of FP reg across call") }, \
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{ "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
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N_("Only preserve 32 bits of FP reg across call") }, \
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{ "parallel-insns", PARALLEL_INSN_FLAG, \
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N_("Enable parallel instructions") }, \
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{ "no-parallel-insns", -PARALLEL_INSN_FLAG, \
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N_("Disable parallel instructions") }, \
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{ "parallel-mpy", PARALLEL_MPY_FLAG, \
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N_("Enable MPY||ADD and MPY||SUB instructions") }, \
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{ "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
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N_("Disable MPY||ADD and MPY||SUB instructions") }, \
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{ "aliases", ALIASES_FLAG, \
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N_("Assume that pointers may be aliased") }, \
|
||||
{ "no-aliases", -ALIASES_FLAG, \
|
||||
N_("Assume that pointers not aliased") }, \
|
||||
{ "", TARGET_DEFAULT, ""} }
|
||||
|
||||
/* Default target switches. */
|
||||
|
||||
/* Play safe, not the fastest code. */
|
||||
#define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_INSN_FLAG \
|
||||
| PARALLEL_MPY_FLAG | RPTB_FLAG
|
||||
|
||||
/* Caveats:
|
||||
Max iteration count for RPTB/RPTS is 2^31 + 1.
|
||||
Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
|
||||
RPTS blocks interrupts. */
|
||||
|
||||
|
||||
extern int target_flags;
|
||||
extern int c4x_rpts_cycles; /* Max cycles for RPTS. */
|
||||
extern int c4x_cpu_version; /* Cpu version C30/31/32/33/40/44. */
|
||||
|
||||
#define TARGET_INLINE (! optimize_size) /* Inline MPYI. */
|
||||
#define TARGET_SMALL_REG_CLASS 0
|
||||
|
||||
#define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
|
||||
#define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
|
||||
#define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
|
||||
#define TARGET_RPTS (target_flags & RPTS_FLAG)
|
||||
#define TARGET_TI (target_flags & TI_FLAG)
|
||||
#define TARGET_PARANOID (target_flags & PARANOID_FLAG)
|
||||
#define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
|
||||
#define TARGET_DEVEL (target_flags & DEVEL_FLAG)
|
||||
#define TARGET_RPTB (target_flags & RPTB_FLAG \
|
||||
&& optimize >= 2)
|
||||
#define TARGET_BK (target_flags & BK_FLAG)
|
||||
#define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG))
|
||||
#define TARGET_DEBUG (target_flags & DEBUG_FLAG)
|
||||
#define TARGET_HOIST (target_flags & HOIST_FLAG)
|
||||
#define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
|
||||
#define TARGET_FORCE (target_flags & FORCE_FLAG)
|
||||
#define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
|
||||
#define TARGET_PARALLEL ((target_flags & PARALLEL_INSN_FLAG) \
|
||||
&& optimize >= 2)
|
||||
#define TARGET_PARALLEL_MPY (TARGET_PARALLEL \
|
||||
&& (target_flags & PARALLEL_MPY_FLAG))
|
||||
#define TARGET_ALIASES (target_flags & ALIASES_FLAG)
|
||||
#define TARGET_C3X (c4x_cpu_version >= 30 \
|
||||
&& c4x_cpu_version <= 39)
|
||||
|
||||
#define TARGET_C3X (target_flags & C3X_FLAG)
|
||||
#define TARGET_C30 (target_flags & C30_FLAG)
|
||||
#define TARGET_C31 (target_flags & C31_FLAG)
|
||||
#define TARGET_C32 (target_flags & C32_FLAG)
|
||||
#define TARGET_C33 (target_flags & C33_FLAG)
|
||||
#define TARGET_C40 (target_flags & C40_FLAG)
|
||||
#define TARGET_C44 (target_flags & C44_FLAG)
|
||||
#define TARGET_C30 (c4x_cpu_version == 30)
|
||||
#define TARGET_C31 (c4x_cpu_version == 31)
|
||||
#define TARGET_C32 (c4x_cpu_version == 32)
|
||||
#define TARGET_C33 (c4x_cpu_version == 33)
|
||||
#define TARGET_C40 (c4x_cpu_version == 40)
|
||||
#define TARGET_C44 (c4x_cpu_version == 44)
|
||||
|
||||
/* Nonzero to use load_immed_addr pattern rather than forcing memory
|
||||
addresses into memory. */
|
||||
@ -321,16 +162,6 @@ extern int target_flags;
|
||||
|
||||
#define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
|
||||
|
||||
/* -mcpu=XX with XX = target DSP version number. */
|
||||
|
||||
extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
|
||||
|
||||
#define TARGET_OPTIONS \
|
||||
{ {"rpts=", &c4x_rpts_cycles_string, \
|
||||
N_("Specify maximum number of iterations for RPTS"), 0}, \
|
||||
{"cpu=", &c4x_cpu_version_string, \
|
||||
N_("Select CPU to generate code for"), 0} }
|
||||
|
||||
/* Sometimes certain combinations of command options do not make sense
|
||||
on a particular target machine. You can define a macro
|
||||
`OVERRIDE_OPTIONS' to take account of this. This macro, if
|
||||
|
||||
140
gcc/config/c4x/c4x.opt
Normal file
140
gcc/config/c4x/c4x.opt
Normal file
@ -0,0 +1,140 @@
|
||||
; Options for the TMS320C[34]x port of the compiler.
|
||||
|
||||
; Copyright (C) 2005 Free Software Foundation, Inc.
|
||||
;
|
||||
; This file is part of GCC.
|
||||
;
|
||||
; GCC is free software; you can redistribute it and/or modify it under
|
||||
; the terms of the GNU General Public License as published by the Free
|
||||
; Software Foundation; either version 2, or (at your option) any later
|
||||
; version.
|
||||
;
|
||||
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
; for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with GCC; see the file COPYING. If not, write to the Free
|
||||
; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
|
||||
; 02111-1307, USA.
|
||||
|
||||
m30
|
||||
Target RejectNegative
|
||||
Generate code for C30 CPU
|
||||
|
||||
m31
|
||||
Target RejectNegative
|
||||
Generate code for C31 CPU
|
||||
|
||||
m32
|
||||
Target RejectNegative
|
||||
Generate code for C32 CPU
|
||||
|
||||
m33
|
||||
Target RejectNegative
|
||||
Generate code for C33 CPU
|
||||
|
||||
m40
|
||||
Target RejectNegative
|
||||
Generate code for C40 CPU
|
||||
|
||||
m44
|
||||
Target RejectNegative
|
||||
Generate code for C44 CPU
|
||||
|
||||
maliases
|
||||
Target Report Mask(ALIASES)
|
||||
Assume that pointers may be aliased
|
||||
|
||||
mbig
|
||||
Target RejectNegative Report InverseMask(SMALL)
|
||||
Big memory model
|
||||
|
||||
mbk
|
||||
Target Report Mask(BK)
|
||||
Use the BK register as a general purpose register
|
||||
|
||||
mcpu=
|
||||
Target RejectNegative Joined
|
||||
-mcpu=CPU Generate code for CPU
|
||||
|
||||
mdb
|
||||
Target Report Mask(DB)
|
||||
Enable use of DB instruction
|
||||
|
||||
mdebug
|
||||
Target Report Mask(DEBUG)
|
||||
Enable debugging
|
||||
|
||||
mdevel
|
||||
Target Report Mask(DEVEL)
|
||||
Enable new features under development
|
||||
|
||||
mfast-fix
|
||||
Target Report Mask(FAST_FIX)
|
||||
Use fast but approximate float to integer conversion
|
||||
|
||||
mforce
|
||||
Target Report Mask(FORCE)
|
||||
Force RTL generation to emit valid 3 operand insns
|
||||
|
||||
mhoist
|
||||
Target Report Mask(HOIST)
|
||||
Force constants into registers to improve hoisting
|
||||
|
||||
misr-dp-reload
|
||||
Target Mask(PARANOID) MaskExists
|
||||
Save DP across ISR in small memory model
|
||||
|
||||
mloop-unsigned
|
||||
Target Report Mask(LOOP_UNSIGNED)
|
||||
Allow unsigned iteration counts for RPTB/DB
|
||||
|
||||
mmemparm
|
||||
Target RejectNegative Report Mask(MEMPARM)
|
||||
Pass arguments on the stack
|
||||
|
||||
mmpyi
|
||||
Target Report Mask(MPYI)
|
||||
Use MPYI instruction for C3x
|
||||
|
||||
mparallel-insns
|
||||
Target Report Mask(PARALLEL)
|
||||
Enable parallel instructions
|
||||
|
||||
mparallel-mpy
|
||||
Target Report Mask(PARALLEL_MPY)
|
||||
Enable MPY||ADD and MPY||SUB instructions
|
||||
|
||||
mparanoid
|
||||
Target Report Mask(PARANOID)
|
||||
Save DP across ISR in small memory model
|
||||
|
||||
mpreserve-float
|
||||
Target Report Mask(PRESERVE_FLOAT)
|
||||
Preserve all 40 bits of FP reg across call
|
||||
|
||||
mregparm
|
||||
Target RejectNegative Report InverseMask(MEMPARM)
|
||||
Pass arguments in registers
|
||||
|
||||
mrptb
|
||||
Target Report Mask(RPTB)
|
||||
Enable use of RTPB instruction
|
||||
|
||||
mrpts
|
||||
Target Report Mask(RPTS)
|
||||
Enable use of RTPS instruction
|
||||
|
||||
mrpts=
|
||||
Target RejectNegative Joined UInteger
|
||||
-mrpts=N Set the maximum number of iterations for RPTS to N
|
||||
|
||||
msmall
|
||||
Target RejectNegative Report Mask(SMALL)
|
||||
Small memory model
|
||||
|
||||
mti
|
||||
Target Report Mask(TI)
|
||||
Emit code compatible with TI tools
|
||||
Loading…
Reference in New Issue
Block a user