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i386.h (VALID_FP_MODE_P): XFmode is invalid on x86_64. 

* i386.h (VALID_FP_MODE_P): XFmode is invalid on x86_64.
	(MODES_TIEABLE_P): QImodes and DImodes are tiable on x86_64.
	(HARD_REGNO_CALLER_SAVE_MODE): Save QImodes as QImodes for x86_64.
	(STATIC_CHAIN_REGNUM): Set to r10 for x86_64.
	(PIC_OFFSET_TABLE_REGNUM): Set to INVALID_REGNUM for x86_64.
	(LIMIT_RELOAD_CLASS): Avoid limiting of QImodes on x86_64.
	(SECONDARY_OUTPUT_RELOAD_CLASS): No need to QImodes.
	(PUSH_ROUNDING): x86_64 rounds to 64bits.
	(CONSTANT_ADDRESS_P): Accept CONST_DOUBLE.
	(REGPARM_MAX): Set to 6 for x86_64.
	(SSE_REGPARM_MAX): Set to 16 for x86_64.
	* i386.c (hard_regno_mode_ok): QImodes can be in all general purpose
	registers.

	* (patterns that does use upper halves): Update constraints
	'q' to 'Q' and 'r' to 'R'.
	(cmpqi_ext_1): Disable for 64bit.
	(cmpqi_ext_3_insn): Likewise.
	(movqi_extzv_1): Likewsie.
	(addqi_ext_1): Liekwsie
	(testqi_ext_1): Liekwsie
	(andqi_ext_1): Liekwsie
	(xorqi_ext_1): Liekwsie
	(cmpqi_ext_1_rex64): New.
	(cmpqi_ext_3_insn_rex64): Likewise.
	(movqi_extzv_1_rex64): Likewsie.
	(addqi_ext_1_rex64): Liekwsie
	(testqi_ext_1_rex64): Liekwsie
	(andqi_ext_1_rex64): Liekwsie
	(xorqi_ext_1_rex64): Liekwsie

From-SVN: r40411
This commit is contained in:
Jan Hubicka 2001-03-12 15:18:57 +01:00 committed by Jan Hubicka
parent 6336e96f4e
commit d28362735b
4 changed files with 281 additions and 67 deletions
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33
gcc/ChangeLog
View File

@ -1,3 +1,36 @@
Mon Mar 12 15:16:36 CET 2001 Jan Hubicka <jh@suse.cz>
* i386.h (VALID_FP_MODE_P): XFmode is invalid on x86_64.
(MODES_TIEABLE_P): QImodes and DImodes are tiable on x86_64.
(HARD_REGNO_CALLER_SAVE_MODE): Save QImodes as QImodes for x86_64.
(STATIC_CHAIN_REGNUM): Set to r10 for x86_64.
(PIC_OFFSET_TABLE_REGNUM): Set to INVALID_REGNUM for x86_64.
(LIMIT_RELOAD_CLASS): Avoid limiting of QImodes on x86_64.
(SECONDARY_OUTPUT_RELOAD_CLASS): No need to QImodes.
(PUSH_ROUNDING): x86_64 rounds to 64bits.
(CONSTANT_ADDRESS_P): Accept CONST_DOUBLE.
(REGPARM_MAX): Set to 6 for x86_64.
(SSE_REGPARM_MAX): Set to 16 for x86_64.
* i386.c (hard_regno_mode_ok): QImodes can be in all general purpose
registers.
* (patterns that does use upper halves): Update constraints
'q' to 'Q' and 'r' to 'R'.
(cmpqi_ext_1): Disable for 64bit.
(cmpqi_ext_3_insn): Likewise.
(movqi_extzv_1): Likewsie.
(addqi_ext_1): Liekwsie
(testqi_ext_1): Liekwsie
(andqi_ext_1): Liekwsie
(xorqi_ext_1): Liekwsie
(cmpqi_ext_1_rex64): New.
(cmpqi_ext_3_insn_rex64): Likewise.
(movqi_extzv_1_rex64): Likewsie.
(addqi_ext_1_rex64): Liekwsie
(testqi_ext_1_rex64): Liekwsie
(andqi_ext_1_rex64): Liekwsie
(xorqi_ext_1_rex64): Liekwsie
2001-03-11 Zack Weinberg <zackw@stanford.edu>
* configure.in: Move check for unsigned enumerated bitfields

2
gcc/config/i386/i386.c
View File

@ -9169,7 +9169,7 @@ ix86_hard_regno_mode_ok (regno, mode)
return 0;
/* Take care for QImode values - they can be in non-QI regs, but then
they do cause partial register stalls. */
if (regno < 4 || mode != QImode)
if (regno < 4 || mode != QImode || TARGET_64BIT)
return 1;
return reload_in_progress || reload_completed || !TARGET_PARTIAL_REG_STALL;
}

57
gcc/config/i386/i386.h
View File

@ -861,9 +861,9 @@ extern int ix86_arch;
#define VALID_FP_MODE_P(mode) \
((mode) == SFmode || (mode) == DFmode || (mode) == TFmode \
|| (mode) == XFmode \
|| (!TARGET_64BIT && (mode) == XFmode) \
|| (mode) == SCmode || (mode) == DCmode || (mode) == TCmode\
|| (mode) == XCmode)
|| (!TARGET_64BIT && (mode) == XCmode))
#define VALID_INT_MODE_P(mode) \
((mode) == QImode || (mode) == HImode || (mode) == SImode \
@ -883,8 +883,15 @@ extern int ix86_arch;
#define MODES_TIEABLE_P(MODE1, MODE2) \
((MODE1) == (MODE2) \
|| ((MODE1) == SImode && (MODE2) == HImode) \
|| ((MODE1) == HImode && (MODE2) == SImode))
|| (((MODE1) == HImode || (MODE1) == SImode \
|| ((MODE1) == QImode \
&& (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
|| ((MODE1) == DImode && TARGET_64BIT)) \
&& ((MODE2) == HImode || (MODE2) == SImode \
|| ((MODE1) == QImode \
&& (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
|| ((MODE2) == DImode && TARGET_64BIT))))
/* Specify the modes required to caller save a given hard regno.
We do this on i386 to prevent flags from being saved at all.
@ -896,8 +903,8 @@ extern int ix86_arch;
: (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
: (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
: (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
: (MODE) == QImode && (REGNO) >= 4 ? SImode : (MODE))
: (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
: (MODE))
/* Specify the registers used for certain standard purposes.
The values of these macros are register numbers. */
@ -955,12 +962,17 @@ extern int ix86_arch;
/* Base register for access to arguments of the function. */
#define ARG_POINTER_REGNUM 16
/* Register in which static-chain is passed to a function. */
#define STATIC_CHAIN_REGNUM 2
/* Register in which static-chain is passed to a function.
We do use ECX as static chain register for 32 bit ABI. On the
64bit ABI, ECX is an argument register, so we use R10 instead. */
#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
/* Register to hold the addressing base for position independent
code access to data items. */
#define PIC_OFFSET_TABLE_REGNUM 3
code access to data items.
We don't use PIC pointer for 64bit mode. Define the regnum to
dummy value to prevent gcc from pesimizing code dealing with EBX.
*/
#define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
/* Register in which address to store a structure value
arrives in the function. On the 386, the prologue
@ -1239,8 +1251,9 @@ enum reg_class
is necessary to be able to hold a value of mode MODE in a reload
register for which class CLASS would ordinarily be used. */
#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
((MODE) == QImode && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
((MODE) == QImode && !TARGET_64BIT \
&& ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
? Q_REGS : (CLASS))
/* Given an rtx X being reloaded into a reg required to be
@ -1269,7 +1282,8 @@ enum reg_class
pseudo. */
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
((CLASS) == GENERAL_REGS && (MODE) == QImode ? Q_REGS : NO_REGS)
((CLASS) == GENERAL_REGS && !TARGET_64BIT && (MODE) == QImode \
? Q_REGS : NO_REGS)
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
@ -1340,9 +1354,15 @@ enum reg_class
this says how many the stack pointer really advances by.
On 386 pushw decrements by exactly 2 no matter what the position was.
On the 386 there is no pushb; we use pushw instead, and this
has the effect of rounding up to 2. */
has the effect of rounding up to 2.
For 64bit ABI we round up to 8 bytes.
*/
#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2))
#define PUSH_ROUNDING(BYTES) \
(TARGET_64BIT \
? (((BYTES) + 7) & (-8)) \
: (((BYTES) + 1) & (-2)))
/* If defined, the maximum amount of space required for outgoing arguments will
be computed and placed into the variable
@ -1803,7 +1823,8 @@ pop{l} %0" \
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
|| GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
|| GET_CODE (X) == CONST_DOUBLE)
/* Nonzero if the constant value X is a legitimate general operand.
It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
@ -2183,7 +2204,9 @@ while (0)
is also used as the pic register in ELF. So for now, don't allow more than
3 registers to be passed in registers. */
#define REGPARM_MAX 3
#define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
#define SSE_REGPARM_MAX (TARGET_64BIT ? 16 : 0)
/* Specify the machine mode that this machine uses

256
gcc/config/i386/i386.md
View File

@ -1,7 +1,8 @@
;; GCC machine description for IA-32.
;; GCC machine description for IA-32 and x86-64.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
;; Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; x86_64 support added by Jan Hubicka
;;
;; This file is part of GNU CC.
;;
@ -1165,13 +1166,27 @@
(define_insn "*cmpqi_ext_1"
[(set (reg 17)
(compare
(match_operand:QI 0 "general_operand" "qm")
(match_operand:QI 0 "general_operand" "Qm")
(subreg:QI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "q")
(match_operand 1 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)) 0)))]
"ix86_match_ccmode (insn, CCmode)"
"!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\\t{%h1, %0|%0, %h1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")])
(define_insn "*cmpqi_ext_1_rex64"
[(set (reg 17)
(compare
(match_operand:QI 0 "ext_register_operand" "Q")
(subreg:QI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)) 0)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\\t{%h1, %0|%0, %h1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")])
@ -1181,7 +1196,7 @@
(compare
(subreg:QI
(zero_extract:SI
(match_operand 0 "ext_register_operand" "q")
(match_operand 0 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)) 0)
(match_operand:QI 1 "const0_operand" "n")))]
@ -1196,10 +1211,10 @@
(compare:CC
(subreg:QI
(zero_extract:SI
(match_operand 0 "ext_register_operand" "q")
(match_operand 0 "ext_register_operand" "")
(const_int 8)
(const_int 8)) 0)
(match_operand:QI 1 "general_operand" "qmn")))]
(match_operand:QI 1 "general_operand" "")))]
""
"")
@ -1208,11 +1223,25 @@
(compare
(subreg:QI
(zero_extract:SI
(match_operand 0 "ext_register_operand" "q")
(match_operand 0 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)) 0)
(match_operand:QI 1 "general_operand" "qmn")))]
"ix86_match_ccmode (insn, CCmode)"
(match_operand:QI 1 "general_operand" "Qmn")))]
"!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")])
(define_insn "cmpqi_ext_3_insn_rex64"
[(set (reg 17)
(compare
(subreg:QI
(zero_extract:SI
(match_operand 0 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)) 0)
(match_operand:QI 1 "nonmemory_operand" "Qn")))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")])
@ -1222,12 +1251,12 @@
(compare
(subreg:QI
(zero_extract:SI
(match_operand 0 "ext_register_operand" "q")
(match_operand 0 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)) 0)
(subreg:QI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "q")
(match_operand 1 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)) 0)))]
"ix86_match_ccmode (insn, CCmode)"
@ -1995,8 +2024,8 @@
(set_attr "length_immediate" "0")])
(define_insn "*movsi_extv_1"
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extract:SI (match_operand:SI 1 "register_operand" "q")
[(set (match_operand:SI 0 "register_operand" "=R")
(sign_extract:SI (match_operand:SI 1 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)))]
""
@ -2005,8 +2034,8 @@
(set_attr "mode" "SI")])
(define_insn "*movhi_extv_1"
[(set (match_operand:HI 0 "register_operand" "=r")
(sign_extract:HI (match_operand:SI 1 "register_operand" "q")
[(set (match_operand:HI 0 "register_operand" "=R")
(sign_extract:HI (match_operand:SI 1 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)))]
""
@ -2043,8 +2072,8 @@
(const_string "QI")))])
(define_insn "*movsi_extzv_1"
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (match_operand 1 "ext_register_operand" "q")
[(set (match_operand:SI 0 "register_operand" "=R")
(zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)))]
""
@ -2052,12 +2081,12 @@
[(set_attr "type" "imovx")
(set_attr "mode" "SI")])
(define_insn "*movqi_extzv_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?r")
(subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "q,q")
(define_insn "*movqi_extzv_2"
[(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
(subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
(const_int 8)
(const_int 8)) 0))]
""
"!TARGET_64BIT"
"*
{
switch (get_attr_type (insn))
@ -2080,21 +2109,58 @@
(const_string "SI")
(const_string "QI")))])
(define_insn "*movqi_extzv_2_rex64"
[(set (match_operand:QI 0 "register_operand" "=Q,?R")
(subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
(const_int 8)
(const_int 8)) 0))]
"TARGET_64BIT"
"*
{
switch (get_attr_type (insn))
{
case TYPE_IMOVX:
return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
default:
return \"mov{b}\\t{%h1, %0|%0, %h1}\";
}
}"
[(set (attr "type")
(if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
(ne (symbol_ref "TARGET_MOVX")
(const_int 0)))
(const_string "imovx")
(const_string "imov")))
(set (attr "mode")
(if_then_else (eq_attr "type" "imovx")
(const_string "SI")
(const_string "QI")))])
(define_insn "*movsi_insv_1"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+q")
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
(const_int 8)
(const_int 8))
(match_operand:SI 1 "nonimmediate_operand" "qm"))]
""
(match_operand:SI 1 "nonimmediate_operand" "Qm"))]
"!TARGET_64BIT"
"mov{b}\\t{%b1, %h0|%h0, %b1}"
[(set_attr "type" "imov")
(set_attr "mode" "QI")])
(define_insn "*movsi_insv_1_rex64"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
(const_int 8)
(const_int 8))
(match_operand:SI 1 "ext_register_operand" "Q"))]
"TARGET_64BIT"
"mov{b}\\t{%b1, %h0|%h0, %b1}"
[(set_attr "type" "imov")
(set_attr "mode" "QI")])
(define_insn "*movqi_insv_2"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+q")
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
(const_int 8)
(const_int 8))
(and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "q")
(and:SI (lshiftrt:SI (match_operand:SI 1 "ext_register_operand" "Q")
(const_int 8))
(const_int 255)))]
""
@ -5448,7 +5514,42 @@
(const_int 8))
(match_operand:QI 2 "general_operand" "qmn")))
(clobber (reg:CC 17))]
""
"!TARGET_64BIT"
"*
{
switch (get_attr_type (insn))
{
case TYPE_INCDEC:
if (operands[2] == const1_rtx)
return \"inc{b}\\t%h0\";
else if (operands[2] == constm1_rtx
|| (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) == 255))
return \"dec{b}\\t%h0\";
abort();
default:
return \"add{b}\\t{%2, %h0|%h0, %2}\";
}
}"
[(set (attr "type")
(if_then_else (match_operand:QI 2 "incdec_operand" "")
(const_string "incdec")
(const_string "alu")))
(set_attr "mode" "QI")])
(define_insn "*addqi_ext_1_rex64"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(plus:SI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(const_int 8))
(match_operand:QI 2 "nonmemory_operand" "Qn")))
(clobber (reg:CC 17))]
"TARGET_64BIT"
"*
{
switch (get_attr_type (insn))
@ -5473,7 +5574,7 @@
(set_attr "mode" "QI")])
(define_insn "*addqi_ext_2"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(plus:SI
@ -5482,7 +5583,7 @@
(const_int 8)
(const_int 8))
(zero_extract:SI
(match_operand 2 "ext_register_operand" "q")
(match_operand 2 "ext_register_operand" "Q")
(const_int 8)
(const_int 8))))
(clobber (reg:CC 17))]
@ -6238,7 +6339,7 @@
(compare
(and:SI
(zero_extract:SI
(match_operand 0 "ext_register_operand" "q")
(match_operand 0 "ext_register_operand" "Q")
(const_int 8)
(const_int 8))
(match_operand 1 "const_int_operand" "n"))
@ -6256,13 +6357,29 @@
(compare
(and:SI
(zero_extract:SI
(match_operand 0 "ext_register_operand" "q")
(match_operand 0 "ext_register_operand" "Q")
(const_int 8)
(const_int 8))
(zero_extend:SI
(match_operand:QI 1 "nonimmediate_operand" "qm")))
(match_operand:QI 1 "nonimmediate_operand" "Qm")))
(const_int 0)))]
"ix86_match_ccmode (insn, CCNOmode)"
"!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"test{b}\\t{%1, %h0|%h0, %1}"
[(set_attr "type" "test")
(set_attr "mode" "QI")])
(define_insn "*testqi_ext_1_rex64"
[(set (reg 17)
(compare
(and:SI
(zero_extract:SI
(match_operand 0 "ext_register_operand" "Q")
(const_int 8)
(const_int 8))
(zero_extend:SI
(match_operand:QI 1 "ext_register_operand" "Q")))
(const_int 0)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"test{b}\\t{%1, %h0|%h0, %1}"
[(set_attr "type" "test")
(set_attr "mode" "QI")])
@ -6272,11 +6389,11 @@
(compare
(and:SI
(zero_extract:SI
(match_operand 0 "ext_register_operand" "q")
(match_operand 0 "ext_register_operand" "Q")
(const_int 8)
(const_int 8))
(zero_extract:SI
(match_operand 1 "ext_register_operand" "q")
(match_operand 1 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)))
(const_int 0)))]
@ -6566,7 +6683,7 @@
;; for a QImode operand, which of course failed.
(define_insn "andqi_ext_0"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(and:SI
@ -6591,11 +6708,11 @@
(and:SI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(const_int 8)
(const_int 8))
(match_operand 2 "const_int_operand" "n"))
(const_int 0)))
(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(and:SI
@ -6612,7 +6729,7 @@
(set_attr "mode" "QI")])
(define_insn "*andqi_ext_1"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(and:SI
@ -6621,16 +6738,34 @@
(const_int 8)
(const_int 8))
(zero_extend:SI
(match_operand:QI 2 "general_operand" "qm"))))
(match_operand:QI 2 "general_operand" "Qm"))))
(clobber (reg:CC 17))]
""
"!TARGET_64BIT"
"and{b}\\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(define_insn "*andqi_ext_1_rex64"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(and:SI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(const_int 8))
(zero_extend:SI
(match_operand:QI 2 "ext_register_operand" "Q"))))
(clobber (reg:CC 17))]
"TARGET_64BIT"
"and{b}\\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")])
(define_insn "*andqi_ext_2"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(and:SI
@ -6639,7 +6774,7 @@
(const_int 8)
(const_int 8))
(zero_extract:SI
(match_operand 2 "ext_register_operand" "q")
(match_operand 2 "ext_register_operand" "Q")
(const_int 8)
(const_int 8))))
(clobber (reg:CC 17))]
@ -6924,14 +7059,14 @@
(set_attr "mode" "QI,QI,SI")])
(define_insn "*xorqi_ext_1"
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(xor:SI
(zero_extract:SI (match_operand 1 "ext_register_operand" "0")
(const_int 8)
(const_int 8))
(zero_extract:SI (match_operand 2 "ext_register_operand" "q")
(zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
(const_int 8)
(const_int 8))))
(clobber (reg:CC 17))]
@ -6984,7 +7119,28 @@
(xor:SI
(zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
(match_dup 2)))]
"ix86_match_ccmode (insn, CCNOmode)"
"!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"xor{b}\\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
(define_insn "*xorqi_cc_ext_1_rex64"
[(set (reg 17)
(compare
(xor:SI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(const_int 8))
(match_operand:QI 2 "nonmemory_operand" "Qn"))
(const_int 0)))
(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(xor:SI
(zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
(match_dup 2)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"xor{b}\\t{%2, %h0|%h0, %2}"
[(set_attr "type" "alu")
(set_attr "mode" "QI")])
@ -7024,14 +7180,16 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
(neg:DI (match_operand:DI 1 "general_operand" "0")))
(clobber (reg:CC 17))]
"ix86_unary_operator_ok (NEG, DImode, operands)"
"!TARGET_64BIT
&& ix86_unary_operator_ok (NEG, DImode, operands)"
"#")
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(neg:DI (match_operand:DI 1 "general_operand" "")))
(clobber (reg:CC 17))]
"reload_completed"
"reload_completed
&& !TARGET_64BIT"
[(parallel
[(set (reg:CCZ 17)
(compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))