i386.h (VALID_FP_MODE_P): XFmode is invalid on x86_64.
* i386.h (VALID_FP_MODE_P): XFmode is invalid on x86_64. (MODES_TIEABLE_P): QImodes and DImodes are tiable on x86_64. (HARD_REGNO_CALLER_SAVE_MODE): Save QImodes as QImodes for x86_64. (STATIC_CHAIN_REGNUM): Set to r10 for x86_64. (PIC_OFFSET_TABLE_REGNUM): Set to INVALID_REGNUM for x86_64. (LIMIT_RELOAD_CLASS): Avoid limiting of QImodes on x86_64. (SECONDARY_OUTPUT_RELOAD_CLASS): No need to QImodes. (PUSH_ROUNDING): x86_64 rounds to 64bits. (CONSTANT_ADDRESS_P): Accept CONST_DOUBLE. (REGPARM_MAX): Set to 6 for x86_64. (SSE_REGPARM_MAX): Set to 16 for x86_64. * i386.c (hard_regno_mode_ok): QImodes can be in all general purpose registers. * (patterns that does use upper halves): Update constraints 'q' to 'Q' and 'r' to 'R'. (cmpqi_ext_1): Disable for 64bit. (cmpqi_ext_3_insn): Likewise. (movqi_extzv_1): Likewsie. (addqi_ext_1): Liekwsie (testqi_ext_1): Liekwsie (andqi_ext_1): Liekwsie (xorqi_ext_1): Liekwsie (cmpqi_ext_1_rex64): New. (cmpqi_ext_3_insn_rex64): Likewise. (movqi_extzv_1_rex64): Likewsie. (addqi_ext_1_rex64): Liekwsie (testqi_ext_1_rex64): Liekwsie (andqi_ext_1_rex64): Liekwsie (xorqi_ext_1_rex64): Liekwsie From-SVN: r40411
This commit is contained in:
parent
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@ -1,3 +1,36 @@
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Mon Mar 12 15:16:36 CET 2001 Jan Hubicka <jh@suse.cz>
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* i386.h (VALID_FP_MODE_P): XFmode is invalid on x86_64.
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(MODES_TIEABLE_P): QImodes and DImodes are tiable on x86_64.
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(HARD_REGNO_CALLER_SAVE_MODE): Save QImodes as QImodes for x86_64.
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(STATIC_CHAIN_REGNUM): Set to r10 for x86_64.
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(PIC_OFFSET_TABLE_REGNUM): Set to INVALID_REGNUM for x86_64.
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(LIMIT_RELOAD_CLASS): Avoid limiting of QImodes on x86_64.
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(SECONDARY_OUTPUT_RELOAD_CLASS): No need to QImodes.
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(PUSH_ROUNDING): x86_64 rounds to 64bits.
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(CONSTANT_ADDRESS_P): Accept CONST_DOUBLE.
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(REGPARM_MAX): Set to 6 for x86_64.
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(SSE_REGPARM_MAX): Set to 16 for x86_64.
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* i386.c (hard_regno_mode_ok): QImodes can be in all general purpose
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registers.
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* (patterns that does use upper halves): Update constraints
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'q' to 'Q' and 'r' to 'R'.
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(cmpqi_ext_1): Disable for 64bit.
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(cmpqi_ext_3_insn): Likewise.
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(movqi_extzv_1): Likewsie.
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(addqi_ext_1): Liekwsie
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(testqi_ext_1): Liekwsie
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(andqi_ext_1): Liekwsie
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(xorqi_ext_1): Liekwsie
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(cmpqi_ext_1_rex64): New.
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(cmpqi_ext_3_insn_rex64): Likewise.
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(movqi_extzv_1_rex64): Likewsie.
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(addqi_ext_1_rex64): Liekwsie
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(testqi_ext_1_rex64): Liekwsie
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(andqi_ext_1_rex64): Liekwsie
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(xorqi_ext_1_rex64): Liekwsie
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2001-03-11 Zack Weinberg <zackw@stanford.edu>
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* configure.in: Move check for unsigned enumerated bitfields
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@ -9169,7 +9169,7 @@ ix86_hard_regno_mode_ok (regno, mode)
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return 0;
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/* Take care for QImode values - they can be in non-QI regs, but then
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they do cause partial register stalls. */
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if (regno < 4 || mode != QImode)
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if (regno < 4 || mode != QImode || TARGET_64BIT)
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return 1;
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return reload_in_progress || reload_completed || !TARGET_PARTIAL_REG_STALL;
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}
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@ -861,9 +861,9 @@ extern int ix86_arch;
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#define VALID_FP_MODE_P(mode) \
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((mode) == SFmode || (mode) == DFmode || (mode) == TFmode \
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|| (mode) == XFmode \
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|| (!TARGET_64BIT && (mode) == XFmode) \
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|| (mode) == SCmode || (mode) == DCmode || (mode) == TCmode\
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|| (mode) == XCmode)
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|| (!TARGET_64BIT && (mode) == XCmode))
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#define VALID_INT_MODE_P(mode) \
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((mode) == QImode || (mode) == HImode || (mode) == SImode \
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@ -883,8 +883,15 @@ extern int ix86_arch;
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#define MODES_TIEABLE_P(MODE1, MODE2) \
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((MODE1) == (MODE2) \
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|| ((MODE1) == SImode && (MODE2) == HImode) \
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|| ((MODE1) == HImode && (MODE2) == SImode))
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|| (((MODE1) == HImode || (MODE1) == SImode \
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|| ((MODE1) == QImode \
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&& (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
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|| ((MODE1) == DImode && TARGET_64BIT)) \
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&& ((MODE2) == HImode || (MODE2) == SImode \
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|| ((MODE1) == QImode \
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&& (TARGET_64BIT || !TARGET_PARTIAL_REG_STALL)) \
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|| ((MODE2) == DImode && TARGET_64BIT))))
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/* Specify the modes required to caller save a given hard regno.
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We do this on i386 to prevent flags from being saved at all.
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@ -896,8 +903,8 @@ extern int ix86_arch;
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: (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \
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: (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS)) \
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: (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \
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: (MODE) == QImode && (REGNO) >= 4 ? SImode : (MODE))
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: (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode \
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: (MODE))
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/* Specify the registers used for certain standard purposes.
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The values of these macros are register numbers. */
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@ -955,12 +962,17 @@ extern int ix86_arch;
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/* Base register for access to arguments of the function. */
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#define ARG_POINTER_REGNUM 16
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/* Register in which static-chain is passed to a function. */
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#define STATIC_CHAIN_REGNUM 2
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/* Register in which static-chain is passed to a function.
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We do use ECX as static chain register for 32 bit ABI. On the
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64bit ABI, ECX is an argument register, so we use R10 instead. */
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#define STATIC_CHAIN_REGNUM (TARGET_64BIT ? FIRST_REX_INT_REG + 10 - 8 : 2)
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/* Register to hold the addressing base for position independent
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code access to data items. */
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#define PIC_OFFSET_TABLE_REGNUM 3
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code access to data items.
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We don't use PIC pointer for 64bit mode. Define the regnum to
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dummy value to prevent gcc from pesimizing code dealing with EBX.
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*/
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#define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? INVALID_REGNUM : 3)
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/* Register in which address to store a structure value
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arrives in the function. On the 386, the prologue
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@ -1240,7 +1252,8 @@ enum reg_class
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register for which class CLASS would ordinarily be used. */
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#define LIMIT_RELOAD_CLASS(MODE, CLASS) \
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((MODE) == QImode && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
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((MODE) == QImode && !TARGET_64BIT \
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&& ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \
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? Q_REGS : (CLASS))
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/* Given an rtx X being reloaded into a reg required to be
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@ -1269,7 +1282,8 @@ enum reg_class
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pseudo. */
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#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
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((CLASS) == GENERAL_REGS && (MODE) == QImode ? Q_REGS : NO_REGS)
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((CLASS) == GENERAL_REGS && !TARGET_64BIT && (MODE) == QImode \
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? Q_REGS : NO_REGS)
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/* Return the maximum number of consecutive registers
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needed to represent mode MODE in a register of class CLASS. */
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@ -1340,9 +1354,15 @@ enum reg_class
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this says how many the stack pointer really advances by.
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On 386 pushw decrements by exactly 2 no matter what the position was.
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On the 386 there is no pushb; we use pushw instead, and this
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has the effect of rounding up to 2. */
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has the effect of rounding up to 2.
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#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2))
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For 64bit ABI we round up to 8 bytes.
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*/
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#define PUSH_ROUNDING(BYTES) \
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(TARGET_64BIT \
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? (((BYTES) + 7) & (-8)) \
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: (((BYTES) + 1) & (-2)))
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/* If defined, the maximum amount of space required for outgoing arguments will
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be computed and placed into the variable
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@ -1803,7 +1823,8 @@ pop{l} %0" \
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#define CONSTANT_ADDRESS_P(X) \
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(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
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|| GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
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|| GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
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|| GET_CODE (X) == CONST_DOUBLE)
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/* Nonzero if the constant value X is a legitimate general operand.
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It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
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@ -2183,7 +2204,9 @@ while (0)
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is also used as the pic register in ELF. So for now, don't allow more than
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3 registers to be passed in registers. */
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#define REGPARM_MAX 3
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#define REGPARM_MAX (TARGET_64BIT ? 6 : 3)
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#define SSE_REGPARM_MAX (TARGET_64BIT ? 16 : 0)
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/* Specify the machine mode that this machine uses
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@ -1,7 +1,8 @@
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;; GCC machine description for IA-32.
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;; GCC machine description for IA-32 and x86-64.
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;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
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;; Free Software Foundation, Inc.
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;; Mostly by William Schelter.
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;; x86_64 support added by Jan Hubicka
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;;
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;; This file is part of GNU CC.
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;;
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@ -1165,13 +1166,27 @@
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(define_insn "*cmpqi_ext_1"
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[(set (reg 17)
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(compare
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(match_operand:QI 0 "general_operand" "qm")
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(match_operand:QI 0 "general_operand" "Qm")
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(subreg:QI
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(zero_extract:SI
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(match_operand 1 "ext_register_operand" "q")
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(match_operand 1 "ext_register_operand" "Q")
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(const_int 8)
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(const_int 8)) 0)))]
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"ix86_match_ccmode (insn, CCmode)"
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"!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
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"cmp{b}\\t{%h1, %0|%0, %h1}"
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[(set_attr "type" "icmp")
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(set_attr "mode" "QI")])
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(define_insn "*cmpqi_ext_1_rex64"
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[(set (reg 17)
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(compare
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(match_operand:QI 0 "ext_register_operand" "Q")
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(subreg:QI
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(zero_extract:SI
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(match_operand 1 "ext_register_operand" "Q")
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(const_int 8)
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(const_int 8)) 0)))]
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"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
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"cmp{b}\\t{%h1, %0|%0, %h1}"
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[(set_attr "type" "icmp")
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(set_attr "mode" "QI")])
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@ -1181,7 +1196,7 @@
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(compare
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(subreg:QI
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(zero_extract:SI
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(match_operand 0 "ext_register_operand" "q")
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(match_operand 0 "ext_register_operand" "Q")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 1 "const0_operand" "n")))]
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@ -1196,10 +1211,10 @@
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(compare:CC
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(subreg:QI
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(zero_extract:SI
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(match_operand 0 "ext_register_operand" "q")
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(match_operand 0 "ext_register_operand" "")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 1 "general_operand" "qmn")))]
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(match_operand:QI 1 "general_operand" "")))]
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""
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"")
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@ -1208,11 +1223,25 @@
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(compare
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(subreg:QI
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(zero_extract:SI
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(match_operand 0 "ext_register_operand" "q")
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(match_operand 0 "ext_register_operand" "Q")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 1 "general_operand" "qmn")))]
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"ix86_match_ccmode (insn, CCmode)"
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(match_operand:QI 1 "general_operand" "Qmn")))]
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"!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
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"cmp{b}\\t{%1, %h0|%h0, %1}"
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[(set_attr "type" "icmp")
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(set_attr "mode" "QI")])
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(define_insn "cmpqi_ext_3_insn_rex64"
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[(set (reg 17)
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(compare
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(subreg:QI
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(zero_extract:SI
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(match_operand 0 "ext_register_operand" "Q")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 1 "nonmemory_operand" "Qn")))]
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"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
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"cmp{b}\\t{%1, %h0|%h0, %1}"
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[(set_attr "type" "icmp")
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(set_attr "mode" "QI")])
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@ -1222,12 +1251,12 @@
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(compare
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(subreg:QI
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(zero_extract:SI
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(match_operand 0 "ext_register_operand" "q")
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(match_operand 0 "ext_register_operand" "Q")
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(const_int 8)
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(const_int 8)) 0)
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(subreg:QI
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(zero_extract:SI
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(match_operand 1 "ext_register_operand" "q")
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(match_operand 1 "ext_register_operand" "Q")
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(const_int 8)
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(const_int 8)) 0)))]
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"ix86_match_ccmode (insn, CCmode)"
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@ -1995,8 +2024,8 @@
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(set_attr "length_immediate" "0")])
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(define_insn "*movsi_extv_1"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(sign_extract:SI (match_operand:SI 1 "register_operand" "q")
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[(set (match_operand:SI 0 "register_operand" "=R")
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(sign_extract:SI (match_operand:SI 1 "ext_register_operand" "Q")
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(const_int 8)
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(const_int 8)))]
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""
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@ -2005,8 +2034,8 @@
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(set_attr "mode" "SI")])
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(define_insn "*movhi_extv_1"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(sign_extract:HI (match_operand:SI 1 "register_operand" "q")
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[(set (match_operand:HI 0 "register_operand" "=R")
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(sign_extract:HI (match_operand:SI 1 "ext_register_operand" "Q")
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(const_int 8)
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(const_int 8)))]
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""
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@ -2043,8 +2072,8 @@
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(const_string "QI")))])
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(define_insn "*movsi_extzv_1"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extract:SI (match_operand 1 "ext_register_operand" "q")
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[(set (match_operand:SI 0 "register_operand" "=R")
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(zero_extract:SI (match_operand 1 "ext_register_operand" "Q")
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(const_int 8)
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(const_int 8)))]
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""
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@ -2052,12 +2081,12 @@
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[(set_attr "type" "imovx")
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(set_attr "mode" "SI")])
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(define_insn "*movqi_extzv_1"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?r")
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(subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "q,q")
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(define_insn "*movqi_extzv_2"
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[(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?R")
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(subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
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(const_int 8)
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(const_int 8)) 0))]
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""
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"!TARGET_64BIT"
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"*
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{
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switch (get_attr_type (insn))
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@ -2080,21 +2109,58 @@
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(const_string "SI")
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(const_string "QI")))])
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(define_insn "*movqi_extzv_2_rex64"
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[(set (match_operand:QI 0 "register_operand" "=Q,?R")
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(subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q,Q")
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(const_int 8)
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(const_int 8)) 0))]
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"TARGET_64BIT"
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"*
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{
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switch (get_attr_type (insn))
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{
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case TYPE_IMOVX:
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return \"movz{bl|x}\\t{%h1, %k0|%k0, %h1}\";
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default:
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return \"mov{b}\\t{%h1, %0|%0, %h1}\";
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}
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}"
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[(set (attr "type")
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(if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
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(ne (symbol_ref "TARGET_MOVX")
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(const_int 0)))
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(const_string "imovx")
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(const_string "imov")))
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(set (attr "mode")
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(if_then_else (eq_attr "type" "imovx")
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(const_string "SI")
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(const_string "QI")))])
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(define_insn "*movsi_insv_1"
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[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+q")
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[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
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(const_int 8)
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(const_int 8))
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(match_operand:SI 1 "nonimmediate_operand" "qm"))]
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""
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(match_operand:SI 1 "nonimmediate_operand" "Qm"))]
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"!TARGET_64BIT"
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"mov{b}\\t{%b1, %h0|%h0, %b1}"
|
||||
[(set_attr "type" "imov")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_insn "*movsi_insv_1_rex64"
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(match_operand:SI 1 "ext_register_operand" "Q"))]
|
||||
"TARGET_64BIT"
|
||||
"mov{b}\\t{%b1, %h0|%h0, %b1}"
|
||||
[(set_attr "type" "imov")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_insn "*movqi_insv_2"
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+q")
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "q")
|
||||
(and:SI (lshiftrt:SI (match_operand:SI 1 "ext_register_operand" "Q")
|
||||
(const_int 8))
|
||||
(const_int 255)))]
|
||||
""
|
||||
@ -5448,7 +5514,42 @@
|
||||
(const_int 8))
|
||||
(match_operand:QI 2 "general_operand" "qmn")))
|
||||
(clobber (reg:CC 17))]
|
||||
""
|
||||
"!TARGET_64BIT"
|
||||
"*
|
||||
{
|
||||
switch (get_attr_type (insn))
|
||||
{
|
||||
case TYPE_INCDEC:
|
||||
if (operands[2] == const1_rtx)
|
||||
return \"inc{b}\\t%h0\";
|
||||
else if (operands[2] == constm1_rtx
|
||||
|| (GET_CODE (operands[2]) == CONST_INT
|
||||
&& INTVAL (operands[2]) == 255))
|
||||
return \"dec{b}\\t%h0\";
|
||||
abort();
|
||||
|
||||
default:
|
||||
return \"add{b}\\t{%2, %h0|%h0, %2}\";
|
||||
}
|
||||
}"
|
||||
[(set (attr "type")
|
||||
(if_then_else (match_operand:QI 2 "incdec_operand" "")
|
||||
(const_string "incdec")
|
||||
(const_string "alu")))
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_insn "*addqi_ext_1_rex64"
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(plus:SI
|
||||
(zero_extract:SI
|
||||
(match_operand 1 "ext_register_operand" "0")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(match_operand:QI 2 "nonmemory_operand" "Qn")))
|
||||
(clobber (reg:CC 17))]
|
||||
"TARGET_64BIT"
|
||||
"*
|
||||
{
|
||||
switch (get_attr_type (insn))
|
||||
@ -5473,7 +5574,7 @@
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_insn "*addqi_ext_2"
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(plus:SI
|
||||
@ -5482,7 +5583,7 @@
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(zero_extract:SI
|
||||
(match_operand 2 "ext_register_operand" "q")
|
||||
(match_operand 2 "ext_register_operand" "Q")
|
||||
(const_int 8)
|
||||
(const_int 8))))
|
||||
(clobber (reg:CC 17))]
|
||||
@ -6238,7 +6339,7 @@
|
||||
(compare
|
||||
(and:SI
|
||||
(zero_extract:SI
|
||||
(match_operand 0 "ext_register_operand" "q")
|
||||
(match_operand 0 "ext_register_operand" "Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(match_operand 1 "const_int_operand" "n"))
|
||||
@ -6256,13 +6357,29 @@
|
||||
(compare
|
||||
(and:SI
|
||||
(zero_extract:SI
|
||||
(match_operand 0 "ext_register_operand" "q")
|
||||
(match_operand 0 "ext_register_operand" "Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(zero_extend:SI
|
||||
(match_operand:QI 1 "nonimmediate_operand" "qm")))
|
||||
(match_operand:QI 1 "nonimmediate_operand" "Qm")))
|
||||
(const_int 0)))]
|
||||
"ix86_match_ccmode (insn, CCNOmode)"
|
||||
"!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
|
||||
"test{b}\\t{%1, %h0|%h0, %1}"
|
||||
[(set_attr "type" "test")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_insn "*testqi_ext_1_rex64"
|
||||
[(set (reg 17)
|
||||
(compare
|
||||
(and:SI
|
||||
(zero_extract:SI
|
||||
(match_operand 0 "ext_register_operand" "Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(zero_extend:SI
|
||||
(match_operand:QI 1 "ext_register_operand" "Q")))
|
||||
(const_int 0)))]
|
||||
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
|
||||
"test{b}\\t{%1, %h0|%h0, %1}"
|
||||
[(set_attr "type" "test")
|
||||
(set_attr "mode" "QI")])
|
||||
@ -6272,11 +6389,11 @@
|
||||
(compare
|
||||
(and:SI
|
||||
(zero_extract:SI
|
||||
(match_operand 0 "ext_register_operand" "q")
|
||||
(match_operand 0 "ext_register_operand" "Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(zero_extract:SI
|
||||
(match_operand 1 "ext_register_operand" "q")
|
||||
(match_operand 1 "ext_register_operand" "Q")
|
||||
(const_int 8)
|
||||
(const_int 8)))
|
||||
(const_int 0)))]
|
||||
@ -6566,7 +6683,7 @@
|
||||
;; for a QImode operand, which of course failed.
|
||||
|
||||
(define_insn "andqi_ext_0"
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(and:SI
|
||||
@ -6595,7 +6712,7 @@
|
||||
(const_int 8))
|
||||
(match_operand 2 "const_int_operand" "n"))
|
||||
(const_int 0)))
|
||||
(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
|
||||
(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(and:SI
|
||||
@ -6612,7 +6729,7 @@
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_insn "*andqi_ext_1"
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(and:SI
|
||||
@ -6621,16 +6738,34 @@
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(zero_extend:SI
|
||||
(match_operand:QI 2 "general_operand" "qm"))))
|
||||
(match_operand:QI 2 "general_operand" "Qm"))))
|
||||
(clobber (reg:CC 17))]
|
||||
""
|
||||
"!TARGET_64BIT"
|
||||
"and{b}\\t{%2, %h0|%h0, %2}"
|
||||
[(set_attr "type" "alu")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_insn "*andqi_ext_1_rex64"
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(and:SI
|
||||
(zero_extract:SI
|
||||
(match_operand 1 "ext_register_operand" "0")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(zero_extend:SI
|
||||
(match_operand:QI 2 "ext_register_operand" "Q"))))
|
||||
(clobber (reg:CC 17))]
|
||||
"TARGET_64BIT"
|
||||
"and{b}\\t{%2, %h0|%h0, %2}"
|
||||
[(set_attr "type" "alu")
|
||||
(set_attr "length_immediate" "0")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_insn "*andqi_ext_2"
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(and:SI
|
||||
@ -6639,7 +6774,7 @@
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(zero_extract:SI
|
||||
(match_operand 2 "ext_register_operand" "q")
|
||||
(match_operand 2 "ext_register_operand" "Q")
|
||||
(const_int 8)
|
||||
(const_int 8))))
|
||||
(clobber (reg:CC 17))]
|
||||
@ -6924,14 +7059,14 @@
|
||||
(set_attr "mode" "QI,QI,SI")])
|
||||
|
||||
(define_insn "*xorqi_ext_1"
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
|
||||
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(xor:SI
|
||||
(zero_extract:SI (match_operand 1 "ext_register_operand" "0")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(zero_extract:SI (match_operand 2 "ext_register_operand" "q")
|
||||
(zero_extract:SI (match_operand 2 "ext_register_operand" "Q")
|
||||
(const_int 8)
|
||||
(const_int 8))))
|
||||
(clobber (reg:CC 17))]
|
||||
@ -6984,7 +7119,28 @@
|
||||
(xor:SI
|
||||
(zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
|
||||
(match_dup 2)))]
|
||||
"ix86_match_ccmode (insn, CCNOmode)"
|
||||
"!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
|
||||
"xor{b}\\t{%2, %h0|%h0, %2}"
|
||||
[(set_attr "type" "alu")
|
||||
(set_attr "mode" "QI")])
|
||||
|
||||
(define_insn "*xorqi_cc_ext_1_rex64"
|
||||
[(set (reg 17)
|
||||
(compare
|
||||
(xor:SI
|
||||
(zero_extract:SI
|
||||
(match_operand 1 "ext_register_operand" "0")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(match_operand:QI 2 "nonmemory_operand" "Qn"))
|
||||
(const_int 0)))
|
||||
(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
|
||||
(const_int 8)
|
||||
(const_int 8))
|
||||
(xor:SI
|
||||
(zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
|
||||
(match_dup 2)))]
|
||||
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
|
||||
"xor{b}\\t{%2, %h0|%h0, %2}"
|
||||
[(set_attr "type" "alu")
|
||||
(set_attr "mode" "QI")])
|
||||
@ -7024,14 +7180,16 @@
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
|
||||
(neg:DI (match_operand:DI 1 "general_operand" "0")))
|
||||
(clobber (reg:CC 17))]
|
||||
"ix86_unary_operator_ok (NEG, DImode, operands)"
|
||||
"!TARGET_64BIT
|
||||
&& ix86_unary_operator_ok (NEG, DImode, operands)"
|
||||
"#")
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "")
|
||||
(neg:DI (match_operand:DI 1 "general_operand" "")))
|
||||
(clobber (reg:CC 17))]
|
||||
"reload_completed"
|
||||
"reload_completed
|
||||
&& !TARGET_64BIT"
|
||||
[(parallel
|
||||
[(set (reg:CCZ 17)
|
||||
(compare:CCZ (neg:SI (match_dup 2)) (const_int 0)))
|
||||
|
Loading…
Reference in New Issue
Block a user