24k.md (r24k_unknown_store): Delete special handling for cprestore.
2012-08-06 Sandra Loosemore <sandra@codesourcery.com> Maxim Kuvyrkov <maxim@codesourcery.com> Julian Brown <julian@codesourcery.com> gcc/ * config/mips/24k.md (r24k_unknown_store): Delete special handling for cprestore. (r24k_int_load, r24k_int_arith, r24k_int_mul3, r24k_int_mfhilo) (r24k_int_cop, r24k_int_multi) (r24kf2_1_fcvt_f2i, r24kf2_1_fxfer) (r24kf1_1_fcvt_f2i, r24kf1_1_fxfer): Use mips_store_data_bypass_p instead of store_data_bypass_p. * config/mips/74k.md (r74k_int_store): Delete special handling for cprestore. (r74k_int_load, r74k_int_logical, r74k_int_arith, r74k_int_cmove): Use mips_store_data_bypass_p instead of store_data_bypass_p. Co-Authored-By: Julian Brown <julian@codesourcery.com> Co-Authored-By: Maxim Kuvyrkov <maxim@codesourcery.com> From-SVN: r190189
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@ -1,3 +1,19 @@
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2012-08-06 Sandra Loosemore <sandra@codesourcery.com>
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Maxim Kuvyrkov <maxim@codesourcery.com>
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Julian Brown <julian@codesourcery.com>
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* config/mips/24k.md (r24k_unknown_store): Delete special handling
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for cprestore.
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(r24k_int_load, r24k_int_arith, r24k_int_mul3, r24k_int_mfhilo)
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(r24k_int_cop, r24k_int_multi)
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(r24kf2_1_fcvt_f2i, r24kf2_1_fxfer)
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(r24kf1_1_fcvt_f2i, r24kf1_1_fxfer): Use mips_store_data_bypass_p
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instead of store_data_bypass_p.
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* config/mips/74k.md (r74k_int_store): Delete special handling for
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cprestore.
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(r74k_int_load, r74k_int_logical, r74k_int_arith, r74k_int_cmove):
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Use mips_store_data_bypass_p instead of store_data_bypass_p.
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2012-08-06 Marc Glisse <marc.glisse@inria.fr>
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2012-08-06 Marc Glisse <marc.glisse@inria.fr>
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PR tree-optimization/51938
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PR tree-optimization/51938
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@ -122,18 +122,7 @@
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;; 6. Store
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;; 6. Store
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(define_insn_reservation "r24k_int_store" 1
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(define_insn_reservation "r24k_int_store" 1
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(and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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(and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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(and (eq_attr "type" "store")
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(eq_attr "type" "store"))
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(eq_attr "mode" "!unknown")))
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"r24k_iss+r24k_ixu_arith")
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;; 6.1 Special case - matches the cprestore pattern which don't set the mode
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;; attrib. This avoids being set as r24k_int_store and have it checked
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;; against store_data_bypass_p, which would then fail because cprestore
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;; does not have a normal SET pattern.
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(define_insn_reservation "r24k_unknown_store" 1
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(and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
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(and (eq_attr "type" "store")
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(eq_attr "mode" "unknown")))
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"r24k_iss+r24k_ixu_arith")
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"r24k_iss+r24k_ixu_arith")
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@ -169,7 +158,7 @@
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;; load->store base: 3 cycles
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;; load->store base: 3 cycles
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;; load->prefetch: 3 cycles
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;; load->prefetch: 3 cycles
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(define_bypass 3 "r24k_int_load" "r24k_int_load")
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(define_bypass 3 "r24k_int_load" "r24k_int_load")
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(define_bypass 3 "r24k_int_load" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 3 "r24k_int_load" "r24k_int_store" "!mips_store_data_bypass_p")
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(define_bypass 3 "r24k_int_load" "r24k_int_prefetch")
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(define_bypass 3 "r24k_int_load" "r24k_int_prefetch")
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;; arith->next use : 1 cycles (Default)
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;; arith->next use : 1 cycles (Default)
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@ -177,14 +166,14 @@
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;; arith->store base: 2 cycles
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;; arith->store base: 2 cycles
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;; arith->prefetch: 2 cycles
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;; arith->prefetch: 2 cycles
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(define_bypass 2 "r24k_int_arith" "r24k_int_load")
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(define_bypass 2 "r24k_int_arith" "r24k_int_load")
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(define_bypass 2 "r24k_int_arith" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 2 "r24k_int_arith" "r24k_int_store" "!mips_store_data_bypass_p")
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(define_bypass 2 "r24k_int_arith" "r24k_int_prefetch")
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(define_bypass 2 "r24k_int_arith" "r24k_int_prefetch")
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;; mul3->next use : 5 cycles (default)
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;; mul3->next use : 5 cycles (default)
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;; mul3->l/s base : 6 cycles
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;; mul3->l/s base : 6 cycles
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;; mul3->prefetch : 6 cycles
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;; mul3->prefetch : 6 cycles
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(define_bypass 6 "r24k_int_mul3" "r24k_int_load")
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(define_bypass 6 "r24k_int_mul3" "r24k_int_load")
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(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!mips_store_data_bypass_p")
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(define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
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(define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
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;; mul3->madd/msub : 1 cycle
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;; mul3->madd/msub : 1 cycle
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@ -195,20 +184,22 @@
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;; mfhilo->prefetch : 6 cycles
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;; mfhilo->prefetch : 6 cycles
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;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo)
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;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo)
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(define_bypass 6 "r24k_int_mfhilo" "r24k_int_load")
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(define_bypass 6 "r24k_int_mfhilo" "r24k_int_load")
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(define_bypass 6 "r24k_int_mfhilo" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 6 "r24k_int_mfhilo" "r24k_int_store"
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"!mips_store_data_bypass_p")
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(define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch")
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(define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch")
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(define_bypass 2 "r24k_int_mthilo" "r24k_int_madd")
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(define_bypass 2 "r24k_int_mthilo" "r24k_int_madd")
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;; cop->next use : 3 cycles (Default)
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;; cop->next use : 3 cycles (Default)
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;; cop->l/s base : 4 cycles
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;; cop->l/s base : 4 cycles
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;; (define_bypass 4 "r24k_int_cop" "r24k_int_load")
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;; (define_bypass 4 "r24k_int_cop" "r24k_int_load")
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;; (define_bypass 4 "r24k_int_cop" "r24k_int_store" "!store_data_bypass_p")
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;; (define_bypass 4 "r24k_int_cop" "r24k_int_store"
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;; "!mips_store_data_bypass_p")
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;; multi->next use : 1 cycles (Default)
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;; multi->next use : 1 cycles (Default)
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;; multi->l/s base : 2 cycles
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;; multi->l/s base : 2 cycles
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;; multi->prefetch : 2 cycles
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;; multi->prefetch : 2 cycles
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(define_bypass 2 "r24k_int_multi" "r24k_int_load")
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(define_bypass 2 "r24k_int_multi" "r24k_int_load")
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(define_bypass 2 "r24k_int_multi" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 2 "r24k_int_multi" "r24k_int_store" "!mips_store_data_bypass_p")
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(define_bypass 2 "r24k_int_multi" "r24k_int_prefetch")
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(define_bypass 2 "r24k_int_multi" "r24k_int_prefetch")
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@ -330,13 +321,14 @@
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;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles
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;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles
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;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles
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;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles
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(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load")
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(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load")
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(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store"
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"!mips_store_data_bypass_p")
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(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch")
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(define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch")
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;; r24kf2_1_fxfer->l/s base : 5 cycles
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;; r24kf2_1_fxfer->l/s base : 5 cycles
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;; r24kf2_1_fxfer->prefetch : 5 cycles
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;; r24kf2_1_fxfer->prefetch : 5 cycles
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(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load")
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(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load")
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(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p")
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(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch")
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(define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch")
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;; --------------------------------------------------------------
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;; --------------------------------------------------------------
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;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles
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;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles
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;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles
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;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles
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(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load")
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(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load")
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(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store"
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"!mips_store_data_bypass_p")
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(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch")
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(define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch")
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;; r24kf1_1_fxfer->l/s base : 3 cycles
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;; r24kf1_1_fxfer->l/s base : 3 cycles
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;; r24kf1_1_fxfer->prefetch : 3 cycles
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;; r24kf1_1_fxfer->prefetch : 3 cycles
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(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load")
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(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load")
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(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!store_data_bypass_p")
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(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p")
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(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch")
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(define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch")
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;; stores
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;; stores
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(define_insn_reservation "r74k_int_store" 1
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(define_insn_reservation "r74k_int_store" 1
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
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(and (eq_attr "type" "store")
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(eq_attr "type" "store"))
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(eq_attr "mode" "!unknown")))
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"r74k_agen")
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"r74k_agen")
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;; load->load base: 4 cycles
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;; load->load base: 4 cycles
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;; load->store base: 4 cycles
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;; load->store base: 4 cycles
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(define_bypass 4 "r74k_int_load" "r74k_int_load")
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(define_bypass 4 "r74k_int_load" "r74k_int_load")
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(define_bypass 4 "r74k_int_load" "r74k_int_store" "!store_data_bypass_p")
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(define_bypass 4 "r74k_int_load" "r74k_int_store" "!mips_store_data_bypass_p")
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;; logical/move/slt/signext->next use : 1 cycles (Default)
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;; logical/move/slt/signext->next use : 1 cycles (Default)
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;; logical/move/slt/signext->load base: 2 cycles
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;; logical/move/slt/signext->load base: 2 cycles
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;; logical/move/slt/signext->store base: 2 cycles
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;; logical/move/slt/signext->store base: 2 cycles
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(define_bypass 2 "r74k_int_logical" "r74k_int_load")
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(define_bypass 2 "r74k_int_logical" "r74k_int_load")
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(define_bypass 2 "r74k_int_logical" "r74k_int_store" "!store_data_bypass_p")
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(define_bypass 2 "r74k_int_logical" "r74k_int_store"
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"!mips_store_data_bypass_p")
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;; arith->next use : 2 cycles (Default)
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;; arith->next use : 2 cycles (Default)
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;; arith->load base: 3 cycles
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;; arith->load base: 3 cycles
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;; arith->store base: 3 cycles
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;; arith->store base: 3 cycles
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(define_bypass 3 "r74k_int_arith" "r74k_int_load")
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(define_bypass 3 "r74k_int_arith" "r74k_int_load")
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(define_bypass 3 "r74k_int_arith" "r74k_int_store" "!store_data_bypass_p")
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(define_bypass 3 "r74k_int_arith" "r74k_int_store" "!mips_store_data_bypass_p")
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;; cmove->next use : 4 cycles (Default)
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;; cmove->next use : 4 cycles (Default)
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;; cmove->load base: 5 cycles
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;; cmove->load base: 5 cycles
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;; cmove->store base: 5 cycles
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;; cmove->store base: 5 cycles
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(define_bypass 5 "r74k_int_cmove" "r74k_int_load")
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(define_bypass 5 "r74k_int_cmove" "r74k_int_load")
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(define_bypass 5 "r74k_int_cmove" "r74k_int_store" "!store_data_bypass_p")
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(define_bypass 5 "r74k_int_cmove" "r74k_int_store"
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"!mips_store_data_bypass_p")
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;; mult/madd/msub->int_mfhilo : 4 cycles (default)
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;; mult/madd/msub->int_mfhilo : 4 cycles (default)
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;; mult->madd/msub : 1 cycles
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;; mult->madd/msub : 1 cycles
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