pa.c: Remove space register specification in memory addresses...
* pa.c: Remove space register specification in memory addresses, except where it is actually needed. * pa.md, pa.h, ee.asm, ee_fp.asm, lib2funcs.asm: Likewise. From-SVN: r26398
This commit is contained in:
parent
da59be1f1f
commit
d2d280851c
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@ -1,3 +1,9 @@
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Tue Apr 13 02:11:11 1999 Jeffrey A Law (law@cygnus.com)
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* pa.c: Remove space register specification in memory addresses,
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except where it is actually needed.
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* pa.md, pa.h, ee.asm, ee_fp.asm, lib2funcs.asm: Likewise.
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Mon Apr 12 23:34:35 PDT 1999 Jeff Law (law@cygnus.com)
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* version.c: Bump for snapshot.
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@ -62,7 +62,7 @@ __outline_prologue
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ldo -4(%r31),%r31
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; Save off %r2
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stw %r2,-20(0,%r30)
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stw %r2,-20(%r30)
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; Make our new frame.
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add %r21,%r30,%r30
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@ -86,37 +86,37 @@ __outline_prologue
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subi 18,%r1,%r1
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blr,n %r1,%r0
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b,n L$0000
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stws,ma %r18,4(0,%r20)
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stws,ma %r18,4(%r20)
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nop
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stws,ma %r17,4(0,%r20)
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stws,ma %r17,4(%r20)
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nop
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stws,ma %r16,4(0,%r20)
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stws,ma %r16,4(%r20)
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nop
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stws,ma %r15,4(0,%r20)
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stws,ma %r15,4(%r20)
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nop
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stws,ma %r14,4(0,%r20)
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stws,ma %r14,4(%r20)
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nop
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stws,ma %r13,4(0,%r20)
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stws,ma %r13,4(%r20)
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nop
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stws,ma %r12,4(0,%r20)
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stws,ma %r12,4(%r20)
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nop
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stws,ma %r11,4(0,%r20)
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stws,ma %r11,4(%r20)
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nop
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stws,ma %r10,4(0,%r20)
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stws,ma %r10,4(%r20)
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nop
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stws,ma %r9,4(0,%r20)
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stws,ma %r9,4(%r20)
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nop
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stws,ma %r8,4(0,%r20)
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stws,ma %r8,4(%r20)
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nop
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stws,ma %r7,4(0,%r20)
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stws,ma %r7,4(%r20)
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nop
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stws,ma %r6,4(0,%r20)
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stws,ma %r6,4(%r20)
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nop
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stws,ma %r5,4(0,%r20)
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stws,ma %r5,4(%r20)
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nop
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stws,ma %r4,4(0,%r20)
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stws,ma %r4,4(%r20)
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nop
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stws,ma %r3,4(0,%r20)
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stws,ma %r3,4(%r20)
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nop
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L$0000
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; All gr saves are done. Align the temporary frame pointer and
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@ -128,25 +128,25 @@ L$0000
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subi 21,%r22,%r22
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blr,n %r22,%r0
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b,n L$0001
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fstws,ma %fr21,8(0,%r20)
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fstws,ma %fr21,8(%r20)
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nop
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fstws,ma %fr20,8(0,%r20)
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fstws,ma %fr20,8(%r20)
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nop
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fstws,ma %fr19,8(0,%r20)
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fstws,ma %fr19,8(%r20)
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nop
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fstws,ma %fr18,8(0,%r20)
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fstws,ma %fr18,8(%r20)
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nop
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fstws,ma %fr17,8(0,%r20)
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fstws,ma %fr17,8(%r20)
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nop
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fstws,ma %fr16,8(0,%r20)
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fstws,ma %fr16,8(%r20)
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nop
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fstws,ma %fr15,8(0,%r20)
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fstws,ma %fr15,8(%r20)
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nop
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fstws,ma %fr14,8(0,%r20)
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fstws,ma %fr14,8(%r20)
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nop
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fstws,ma %fr13,8(0,%r20)
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fstws,ma %fr13,8(%r20)
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nop
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fstws,ma %fr12,8(0,%r20)
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fstws,ma %fr12,8(%r20)
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nop
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L$0001
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; Return
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@ -170,7 +170,7 @@ __outline_epilogue
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ldo -4(%r31),%r31
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; Reload %r2
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ldw -20(0,%r20),%r2
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ldw -20(%r20),%r2
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; Add in local_fsize (%r19) to the frame pointer to find
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; the saved registers.
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@ -191,37 +191,37 @@ __outline_epilogue
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subi 18,%r1,%r1
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blr,n %r1,%r0
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b,n L$0004
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ldws,ma 4(0,%r20),%r18
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ldws,ma 4(%r20),%r18
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nop
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ldws,ma 4(0,%r20),%r17
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ldws,ma 4(%r20),%r17
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nop
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ldws,ma 4(0,%r20),%r16
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ldws,ma 4(%r20),%r16
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nop
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ldws,ma 4(0,%r20),%r15
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ldws,ma 4(%r20),%r15
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nop
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ldws,ma 4(0,%r20),%r14
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ldws,ma 4(%r20),%r14
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nop
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ldws,ma 4(0,%r20),%r13
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ldws,ma 4(%r20),%r13
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nop
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ldws,ma 4(0,%r20),%r12
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ldws,ma 4(%r20),%r12
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nop
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ldws,ma 4(0,%r20),%r11
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ldws,ma 4(%r20),%r11
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nop
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ldws,ma 4(0,%r20),%r10
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ldws,ma 4(%r20),%r10
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nop
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ldws,ma 4(0,%r20),%r9
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ldws,ma 4(%r20),%r9
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nop
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ldws,ma 4(0,%r20),%r8
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ldws,ma 4(%r20),%r8
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nop
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ldws,ma 4(0,%r20),%r7
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ldws,ma 4(%r20),%r7
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nop
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ldws,ma 4(0,%r20),%r6
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ldws,ma 4(%r20),%r6
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nop
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ldws,ma 4(0,%r20),%r5
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ldws,ma 4(%r20),%r5
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nop
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ldws,ma 4(0,%r20),%r4
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ldws,ma 4(%r20),%r4
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nop
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ldws,ma 4(0,%r20),%r3
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ldws,ma 4(%r20),%r3
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nop
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L$0004
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; All gr restore are done. Align the temporary frame pointer and
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@ -233,25 +233,25 @@ L$0004
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subi 21,%r22,%r22
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blr,n %r22,%r0
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b,n L$0005
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fldws,ma 8(0,%r20),%fr21
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fldws,ma 8(%r20),%fr21
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nop
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fldws,ma 8(0,%r20),%fr20
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fldws,ma 8(%r20),%fr20
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nop
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fldws,ma 8(0,%r20),%fr19
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fldws,ma 8(%r20),%fr19
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nop
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fldws,ma 8(0,%r20),%fr18
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fldws,ma 8(%r20),%fr18
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nop
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fldws,ma 8(0,%r20),%fr17
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fldws,ma 8(%r20),%fr17
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nop
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fldws,ma 8(0,%r20),%fr16
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fldws,ma 8(%r20),%fr16
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nop
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fldws,ma 8(0,%r20),%fr15
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fldws,ma 8(%r20),%fr15
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nop
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fldws,ma 8(0,%r20),%fr14
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fldws,ma 8(%r20),%fr14
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nop
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fldws,ma 8(0,%r20),%fr13
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fldws,ma 8(%r20),%fr13
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nop
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fldws,ma 8(0,%r20),%fr12
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fldws,ma 8(%r20),%fr12
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nop
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L$0005
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; Return and deallocate our frame.
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@ -63,13 +63,13 @@ __outline_prologue_fp
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ldo -4(%r31),%r31
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; Save off %r2
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stw %r2,-20(0,%r30)
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stw %r2,-20(%r30)
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; Make our new frame.
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add %r21,%r30,%r30
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; Save our old stack pointer.
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stw %r20,0(0,%r20)
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stw %r20,0(%r20)
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; Add in local_fsize to our frame pointer so we do register
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; saves into the right place
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@ -90,37 +90,37 @@ __outline_prologue_fp
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subi 18,%r1,%r1
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blr,n %r1,%r0
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b,n L$0002
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stws,ma %r18,4(0,%r20)
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stws,ma %r18,4(%r20)
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nop
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stws,ma %r17,4(0,%r20)
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stws,ma %r17,4(%r20)
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nop
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stws,ma %r16,4(0,%r20)
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stws,ma %r16,4(%r20)
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nop
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stws,ma %r15,4(0,%r20)
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stws,ma %r15,4(%r20)
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nop
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stws,ma %r14,4(0,%r20)
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stws,ma %r14,4(%r20)
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nop
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stws,ma %r13,4(0,%r20)
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stws,ma %r13,4(%r20)
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nop
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stws,ma %r12,4(0,%r20)
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stws,ma %r12,4(%r20)
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nop
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stws,ma %r11,4(0,%r20)
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stws,ma %r11,4(%r20)
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nop
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stws,ma %r10,4(0,%r20)
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stws,ma %r10,4(%r20)
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nop
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stws,ma %r9,4(0,%r20)
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stws,ma %r9,4(%r20)
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nop
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stws,ma %r8,4(0,%r20)
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stws,ma %r8,4(%r20)
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nop
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stws,ma %r7,4(0,%r20)
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stws,ma %r7,4(%r20)
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nop
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stws,ma %r6,4(0,%r20)
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stws,ma %r6,4(%r20)
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nop
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stws,ma %r5,4(0,%r20)
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stws,ma %r5,4(%r20)
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nop
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stws,ma %r4,4(0,%r20)
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stws,ma %r4,4(%r20)
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nop
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stws,ma %r3,4(0,%r20)
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stws,ma %r3,4(%r20)
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nop
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L$0002
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; All gr saves are done. Align the temporary frame pointer and
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@ -132,25 +132,25 @@ L$0002
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subi 21,%r22,%r22
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blr,n %r22,%r0
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b,n L$0003
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fstws,ma %fr21,8(0,%r20)
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fstws,ma %fr21,8(%r20)
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nop
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fstws,ma %fr20,8(0,%r20)
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fstws,ma %fr20,8(%r20)
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nop
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fstws,ma %fr19,8(0,%r20)
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fstws,ma %fr19,8(%r20)
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nop
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fstws,ma %fr18,8(0,%r20)
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fstws,ma %fr18,8(%r20)
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nop
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fstws,ma %fr17,8(0,%r20)
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fstws,ma %fr17,8(%r20)
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nop
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fstws,ma %fr16,8(0,%r20)
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fstws,ma %fr16,8(%r20)
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nop
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fstws,ma %fr15,8(0,%r20)
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fstws,ma %fr15,8(%r20)
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nop
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fstws,ma %fr14,8(0,%r20)
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fstws,ma %fr14,8(%r20)
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nop
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fstws,ma %fr13,8(0,%r20)
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fstws,ma %fr13,8(%r20)
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nop
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fstws,ma %fr12,8(0,%r20)
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fstws,ma %fr12,8(%r20)
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nop
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L$0003
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; Return, setting up a frame pointer in the delay slot
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@ -178,10 +178,10 @@ __outline_epilogue_fp
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; Reload %r2
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; First save off %r2
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ldw -20(0,%r20),%r2
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ldw -20(%r20),%r2
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; Load our old stack pointer, save it in %r21.
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ldw 0(0,%r20),%r21
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ldw 0(%r20),%r21
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; Add in local_fsize (%r19) to the frame pointer to find
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; the saved registers.
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@ -202,37 +202,37 @@ __outline_epilogue_fp
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subi 18,%r1,%r1
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blr,n %r1,%r0
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b,n L$0006
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ldws,ma 4(0,%r20),%r18
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ldws,ma 4(%r20),%r18
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nop
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ldws,ma 4(0,%r20),%r17
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ldws,ma 4(%r20),%r17
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nop
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ldws,ma 4(0,%r20),%r16
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ldws,ma 4(%r20),%r16
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nop
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ldws,ma 4(0,%r20),%r15
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ldws,ma 4(%r20),%r15
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nop
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ldws,ma 4(0,%r20),%r14
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ldws,ma 4(%r20),%r14
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nop
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ldws,ma 4(0,%r20),%r13
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ldws,ma 4(%r20),%r13
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nop
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ldws,ma 4(0,%r20),%r12
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ldws,ma 4(%r20),%r12
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nop
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ldws,ma 4(0,%r20),%r11
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ldws,ma 4(%r20),%r11
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nop
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ldws,ma 4(0,%r20),%r10
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ldws,ma 4(%r20),%r10
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nop
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ldws,ma 4(0,%r20),%r9
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ldws,ma 4(%r20),%r9
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nop
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ldws,ma 4(0,%r20),%r8
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ldws,ma 4(%r20),%r8
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nop
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ldws,ma 4(0,%r20),%r7
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ldws,ma 4(%r20),%r7
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nop
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ldws,ma 4(0,%r20),%r6
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ldws,ma 4(%r20),%r6
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nop
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ldws,ma 4(0,%r20),%r5
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ldws,ma 4(%r20),%r5
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nop
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ldws,ma 4(0,%r20),%r4
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ldws,ma 4(%r20),%r4
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nop
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ldws,ma 4(0,%r20),%r3
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ldws,ma 4(%r20),%r3
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nop
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L$0006
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; All gr restore are done. Align the temporary frame pointer and
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@ -244,25 +244,25 @@ L$0006
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subi 21,%r22,%r22
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blr,n %r22,%r0
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b,n L$0007
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fldws,ma 8(0,%r20),%fr21
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fldws,ma 8(%r20),%fr21
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nop
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fldws,ma 8(0,%r20),%fr20
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fldws,ma 8(%r20),%fr20
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nop
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fldws,ma 8(0,%r20),%fr19
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fldws,ma 8(%r20),%fr19
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nop
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fldws,ma 8(0,%r20),%fr18
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fldws,ma 8(%r20),%fr18
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nop
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fldws,ma 8(0,%r20),%fr17
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fldws,ma 8(%r20),%fr17
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nop
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fldws,ma 8(0,%r20),%fr16
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fldws,ma 8(%r20),%fr16
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nop
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fldws,ma 8(0,%r20),%fr15
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fldws,ma 8(%r20),%fr15
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nop
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fldws,ma 8(0,%r20),%fr14
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fldws,ma 8(%r20),%fr14
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nop
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fldws,ma 8(0,%r20),%fr13
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fldws,ma 8(%r20),%fr13
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nop
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fldws,ma 8(0,%r20),%fr12
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fldws,ma 8(%r20),%fr12
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nop
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L$0007
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; Return and deallocate our frame.
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|
|
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@ -50,7 +50,7 @@ __gcc_plt_call
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.CALLINFO
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.ENTRY
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; Our return address comes in %r31, not %r2!
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stw %r31,-8(0,%r30)
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stw %r31,-8(%r30)
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; An inline version of dyncall so we don't have to worry
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; about long calls to millicode, PIC and other complexities.
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|
@ -63,7 +63,7 @@ L$foo
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mtsp %r1,%sr0
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ble 0(%sr0,%r22)
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copy %r31,%r2
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ldw -8(0,%r30),%r2
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ldw -8(%r30),%r2
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; We're going to be returning to a stack address, so we
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; need to do an intra-space return.
|
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|
|
|
@ -1661,8 +1661,8 @@ output_move_double (operands)
|
|||
register. (We do this in a non-obvious way to
|
||||
save a register file writeback) */
|
||||
if (GET_CODE (addr) == POST_INC)
|
||||
return "stws,ma %1,8(0,%0)\n\tstw %R1,-4(0,%0)";
|
||||
return "stws,ma %1,-8(0,%0)\n\tstw %R1,12(0,%0)";
|
||||
return "stws,ma %1,8(%0)\n\tstw %R1,-4(%0)";
|
||||
return "stws,ma %1,-8(%0)\n\tstw %R1,12(%0)";
|
||||
}
|
||||
else
|
||||
abort();
|
||||
|
@ -1681,8 +1681,8 @@ output_move_double (operands)
|
|||
register. (We do this in a non-obvious way to
|
||||
save a register file writeback) */
|
||||
if (GET_CODE (addr) == PRE_INC)
|
||||
return "stws,mb %1,8(0,%0)\n\tstw %R1,4(0,%0)";
|
||||
return "stws,mb %1,-8(0,%0)\n\tstw %R1,4(0,%0)";
|
||||
return "stws,mb %1,8(%0)\n\tstw %R1,4(%0)";
|
||||
return "stws,mb %1,-8(%0)\n\tstw %R1,4(%0)";
|
||||
}
|
||||
else
|
||||
abort();
|
||||
|
@ -1708,8 +1708,8 @@ output_move_double (operands)
|
|||
register. (We do this in a non-obvious way to
|
||||
save a register file writeback) */
|
||||
if (GET_CODE (addr) == POST_INC)
|
||||
return "ldws,ma 8(0,%1),%0\n\tldw -4(0,%1),%R0";
|
||||
return "ldws,ma -8(0,%1),%0\n\tldw 12(0,%1),%R0";
|
||||
return "ldws,ma 8(%1),%0\n\tldw -4(%1),%R0";
|
||||
return "ldws,ma -8(%1),%0\n\tldw 12(%1),%R0";
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1717,8 +1717,8 @@ output_move_double (operands)
|
|||
address register *and* update that register. Probably
|
||||
we don't need to handle this at all. */
|
||||
if (GET_CODE (addr) == POST_INC)
|
||||
return "ldw 4(0,%1),%R0\n\tldws,ma 8(0,%1),%0";
|
||||
return "ldw 4(0,%1),%R0\n\tldws,ma -8(0,%1),%0";
|
||||
return "ldw 4(%1),%R0\n\tldws,ma 8(%1),%0";
|
||||
return "ldw 4(%1),%R0\n\tldws,ma -8(%1),%0";
|
||||
}
|
||||
}
|
||||
else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
|
||||
|
@ -1735,8 +1735,8 @@ output_move_double (operands)
|
|||
register. (We do this in a non-obvious way to
|
||||
save a register file writeback) */
|
||||
if (GET_CODE (addr) == PRE_INC)
|
||||
return "ldws,mb 8(0,%1),%0\n\tldw 4(0,%1),%R0";
|
||||
return "ldws,mb -8(0,%1),%0\n\tldw 4(0,%1),%R0";
|
||||
return "ldws,mb 8(%1),%0\n\tldw 4(%1),%R0";
|
||||
return "ldws,mb -8(%1),%0\n\tldw 4(%1),%R0";
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1744,8 +1744,8 @@ output_move_double (operands)
|
|||
address register *and* update that register. Probably
|
||||
we don't need to handle this at all. */
|
||||
if (GET_CODE (addr) == PRE_INC)
|
||||
return "ldw 12(0,%1),%R0\n\tldws,mb 8(0,%1),%0";
|
||||
return "ldw -4(0,%1),%R0\n\tldws,mb -8(0,%1),%0";
|
||||
return "ldw 12(%1),%R0\n\tldws,mb 8(%1),%0";
|
||||
return "ldw -4(%1),%R0\n\tldws,mb -8(%1),%0";
|
||||
}
|
||||
}
|
||||
else if (GET_CODE (addr) == PLUS
|
||||
|
@ -1762,7 +1762,7 @@ output_move_double (operands)
|
|||
xoperands[2] = XEXP (XEXP (addr, 0), 0);
|
||||
xoperands[3] = XEXP (XEXP (addr, 0), 1);
|
||||
output_asm_insn ("sh%O3addl %2,%1,%0", xoperands);
|
||||
return "ldw 4(0,%0),%R0\n\tldw 0(0,%0),%0";
|
||||
return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1773,7 +1773,7 @@ output_move_double (operands)
|
|||
xoperands[2] = XEXP (XEXP (addr, 0), 0);
|
||||
xoperands[3] = XEXP (XEXP (addr, 0), 1);
|
||||
output_asm_insn ("sh%O3addl %2,%1,%R0", xoperands);
|
||||
return "ldw 0(0,%R0),%0\n\tldw 4(0,%R0),%R0";
|
||||
return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
|
||||
}
|
||||
|
||||
}
|
||||
|
@ -1967,11 +1967,11 @@ output_block_move (operands, size_is_constant)
|
|||
output_asm_insn ("ldi %4,%2", operands);
|
||||
|
||||
/* Copying loop. */
|
||||
output_asm_insn ("ldws,ma 4(0,%1),%3", operands);
|
||||
output_asm_insn ("ldws,ma 4(0,%1),%6", operands);
|
||||
output_asm_insn ("stws,ma %3,4(0,%0)", operands);
|
||||
output_asm_insn ("ldws,ma 4(%1),%3", operands);
|
||||
output_asm_insn ("ldws,ma 4(%1),%6", operands);
|
||||
output_asm_insn ("stws,ma %3,4(%0)", operands);
|
||||
output_asm_insn ("addib,>= -8,%2,.-12", operands);
|
||||
output_asm_insn ("stws,ma %6,4(0,%0)", operands);
|
||||
output_asm_insn ("stws,ma %6,4(%0)", operands);
|
||||
|
||||
/* Handle the residual. There could be up to 7 bytes of
|
||||
residual to copy! */
|
||||
|
@ -1979,13 +1979,13 @@ output_block_move (operands, size_is_constant)
|
|||
{
|
||||
operands[4] = GEN_INT (n_bytes % 4);
|
||||
if (n_bytes % 8 >= 4)
|
||||
output_asm_insn ("ldws,ma 4(0,%1),%3", operands);
|
||||
output_asm_insn ("ldws,ma 4(%1),%3", operands);
|
||||
if (n_bytes % 4 != 0)
|
||||
output_asm_insn ("ldw 0(0,%1),%6", operands);
|
||||
output_asm_insn ("ldw 0(%1),%6", operands);
|
||||
if (n_bytes % 8 >= 4)
|
||||
output_asm_insn ("stws,ma %3,4(0,%0)", operands);
|
||||
output_asm_insn ("stws,ma %3,4(%0)", operands);
|
||||
if (n_bytes % 4 != 0)
|
||||
output_asm_insn ("stbys,e %6,%4(0,%0)", operands);
|
||||
output_asm_insn ("stbys,e %6,%4(%0)", operands);
|
||||
}
|
||||
return "";
|
||||
|
||||
|
@ -1995,23 +1995,23 @@ output_block_move (operands, size_is_constant)
|
|||
output_asm_insn ("ldi %4,%2", operands);
|
||||
|
||||
/* Copying loop. */
|
||||
output_asm_insn ("ldhs,ma 2(0,%1),%3", operands);
|
||||
output_asm_insn ("ldhs,ma 2(0,%1),%6", operands);
|
||||
output_asm_insn ("sths,ma %3,2(0,%0)", operands);
|
||||
output_asm_insn ("ldhs,ma 2(%1),%3", operands);
|
||||
output_asm_insn ("ldhs,ma 2(%1),%6", operands);
|
||||
output_asm_insn ("sths,ma %3,2(%0)", operands);
|
||||
output_asm_insn ("addib,>= -4,%2,.-12", operands);
|
||||
output_asm_insn ("sths,ma %6,2(0,%0)", operands);
|
||||
output_asm_insn ("sths,ma %6,2(%0)", operands);
|
||||
|
||||
/* Handle the residual. */
|
||||
if (n_bytes % 4 != 0)
|
||||
{
|
||||
if (n_bytes % 4 >= 2)
|
||||
output_asm_insn ("ldhs,ma 2(0,%1),%3", operands);
|
||||
output_asm_insn ("ldhs,ma 2(%1),%3", operands);
|
||||
if (n_bytes % 2 != 0)
|
||||
output_asm_insn ("ldb 0(0,%1),%6", operands);
|
||||
output_asm_insn ("ldb 0(%1),%6", operands);
|
||||
if (n_bytes % 4 >= 2)
|
||||
output_asm_insn ("sths,ma %3,2(0,%0)", operands);
|
||||
output_asm_insn ("sths,ma %3,2(%0)", operands);
|
||||
if (n_bytes % 2 != 0)
|
||||
output_asm_insn ("stb %6,0(0,%0)", operands);
|
||||
output_asm_insn ("stb %6,0(%0)", operands);
|
||||
}
|
||||
return "";
|
||||
|
||||
|
@ -2021,17 +2021,17 @@ output_block_move (operands, size_is_constant)
|
|||
output_asm_insn ("ldi %4,%2", operands);
|
||||
|
||||
/* Copying loop. */
|
||||
output_asm_insn ("ldbs,ma 1(0,%1),%3", operands);
|
||||
output_asm_insn ("ldbs,ma 1(0,%1),%6", operands);
|
||||
output_asm_insn ("stbs,ma %3,1(0,%0)", operands);
|
||||
output_asm_insn ("ldbs,ma 1(%1),%3", operands);
|
||||
output_asm_insn ("ldbs,ma 1(%1),%6", operands);
|
||||
output_asm_insn ("stbs,ma %3,1(%0)", operands);
|
||||
output_asm_insn ("addib,>= -2,%2,.-12", operands);
|
||||
output_asm_insn ("stbs,ma %6,1(0,%0)", operands);
|
||||
output_asm_insn ("stbs,ma %6,1(%0)", operands);
|
||||
|
||||
/* Handle the residual. */
|
||||
if (n_bytes % 2 != 0)
|
||||
{
|
||||
output_asm_insn ("ldb 0(0,%1),%3", operands);
|
||||
output_asm_insn ("stb %3,0(0,%0)", operands);
|
||||
output_asm_insn ("ldb 0(%1),%3", operands);
|
||||
output_asm_insn ("stb %3,0(%0)", operands);
|
||||
}
|
||||
return "";
|
||||
|
||||
|
@ -3883,21 +3883,21 @@ print_operand (file, x, code)
|
|||
{
|
||||
case PRE_DEC:
|
||||
case POST_DEC:
|
||||
fprintf (file, "-%d(0,%s)", size, reg_names [REGNO (base)]);
|
||||
fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
|
||||
break;
|
||||
case PRE_INC:
|
||||
case POST_INC:
|
||||
fprintf (file, "%d(0,%s)", size, reg_names [REGNO (base)]);
|
||||
fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
|
||||
break;
|
||||
default:
|
||||
if (GET_CODE (XEXP (x, 0)) == PLUS
|
||||
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
|
||||
fprintf (file, "%s(0,%s)",
|
||||
fprintf (file, "%s(%s)",
|
||||
reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
|
||||
reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
|
||||
else if (GET_CODE (XEXP (x, 0)) == PLUS
|
||||
&& GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
|
||||
fprintf (file, "%s(0,%s)",
|
||||
fprintf (file, "%s(%s)",
|
||||
reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
|
||||
reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
|
||||
else
|
||||
|
@ -4888,10 +4888,10 @@ output_dbra (operands, insn, which_alternative)
|
|||
return "ldo %1(%0),%0";
|
||||
else if (which_alternative == 1)
|
||||
{
|
||||
output_asm_insn ("fstws %0,-16(0,%%r30)",operands);
|
||||
output_asm_insn ("ldw -16(0,%%r30),%4",operands);
|
||||
output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands);
|
||||
return "fldws -16(0,%%r30),%0";
|
||||
output_asm_insn ("fstws %0,-16(%%r30)",operands);
|
||||
output_asm_insn ("ldw -16(%%r30),%4",operands);
|
||||
output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
|
||||
return "fldws -16(%%r30),%0";
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -4953,12 +4953,12 @@ output_dbra (operands, insn, which_alternative)
|
|||
/* Move loop counter from FP register to MEM then into a GR,
|
||||
increment the GR, store the GR into MEM, and finally reload
|
||||
the FP register from MEM from within the branch's delay slot. */
|
||||
output_asm_insn ("fstws %0,-16(0,%%r30)\n\tldw -16(0,%%r30),%4",operands);
|
||||
output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(0,%%r30)", operands);
|
||||
output_asm_insn ("fstws %0,-16(%%r30)\n\tldw -16(%%r30),%4",operands);
|
||||
output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
|
||||
if (get_attr_length (insn) == 24)
|
||||
return "comb,%S2 0,%4,%3\n\tfldws -16(0,%%r30),%0";
|
||||
return "comb,%S2 0,%4,%3\n\tfldws -16(%%r30),%0";
|
||||
else
|
||||
return "comclr,%B2 0,%4,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
|
||||
return "comclr,%B2 0,%4,0\n\tbl %3,0\n\tfldws -16(%%r30),%0";
|
||||
}
|
||||
/* Deal with gross reload from memory case. */
|
||||
else
|
||||
|
@ -4994,8 +4994,8 @@ output_movb (operands, insn, which_alternative, reverse_comparison)
|
|||
return "copy %1,%0";
|
||||
else if (which_alternative == 1)
|
||||
{
|
||||
output_asm_insn ("stw %1,-16(0,%%r30)",operands);
|
||||
return "fldws -16(0,%%r30),%0";
|
||||
output_asm_insn ("stw %1,-16(%%r30)",operands);
|
||||
return "fldws -16(%%r30),%0";
|
||||
}
|
||||
else if (which_alternative == 2)
|
||||
return "stw %1,%0";
|
||||
|
@ -5060,11 +5060,11 @@ output_movb (operands, insn, which_alternative, reverse_comparison)
|
|||
/* Move loop counter from FP register to MEM then into a GR,
|
||||
increment the GR, store the GR into MEM, and finally reload
|
||||
the FP register from MEM from within the branch's delay slot. */
|
||||
output_asm_insn ("stw %1,-16(0,%%r30)",operands);
|
||||
output_asm_insn ("stw %1,-16(%%r30)",operands);
|
||||
if (get_attr_length (insn) == 12)
|
||||
return "comb,%S2 0,%1,%3\n\tfldws -16(0,%%r30),%0";
|
||||
return "comb,%S2 0,%1,%3\n\tfldws -16(%%r30),%0";
|
||||
else
|
||||
return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tfldws -16(0,%%r30),%0";
|
||||
return "comclr,%B2 0,%1,0\n\tbl %3,0\n\tfldws -16(%%r30),%0";
|
||||
}
|
||||
/* Deal with gross reload from memory case. */
|
||||
else if (which_alternative == 2)
|
||||
|
@ -5402,7 +5402,7 @@ output_call (insn, call_dest)
|
|||
|
||||
output_asm_insn ("addil LT%%%0,%%r19", xoperands);
|
||||
output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
|
||||
output_asm_insn ("ldw 0(0,%%r22),%%r22", xoperands);
|
||||
output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
|
||||
|
||||
/* Get our address + 8 into %r1. */
|
||||
output_asm_insn ("bl .+8,%%r1", xoperands);
|
||||
|
|
|
@ -1320,15 +1320,15 @@ extern union tree_node *current_function_decl;
|
|||
|
||||
#define TRAMPOLINE_TEMPLATE(FILE) \
|
||||
{ \
|
||||
fputs ("\tldw 36(0,%r22),%r21\n", FILE); \
|
||||
fputs ("\tldw 36(%r22),%r21\n", FILE); \
|
||||
fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \
|
||||
fputs ("\tdepi 0,31,2,%r21\n", FILE); \
|
||||
fputs ("\tldw 4(0,%r21),%r19\n", FILE); \
|
||||
fputs ("\tldw 0(0,%r21),%r21\n", FILE); \
|
||||
fputs ("\tldsid (0,%r21),%r1\n", FILE); \
|
||||
fputs ("\tldw 4(%r21),%r19\n", FILE); \
|
||||
fputs ("\tldw 0(%r21),%r21\n", FILE); \
|
||||
fputs ("\tldsid (%r21),%r1\n", FILE); \
|
||||
fputs ("\tmtsp %r1,%sr0\n", FILE); \
|
||||
fputs ("\tbe 0(%sr0,%r21)\n", FILE); \
|
||||
fputs ("\tldw 40(0,%r22),%r29\n", FILE); \
|
||||
fputs ("\tldw 40(%r22),%r29\n", FILE); \
|
||||
fputs ("\t.word 0\n", FILE); \
|
||||
fputs ("\t.word 0\n", FILE); \
|
||||
}
|
||||
|
@ -2429,7 +2429,7 @@ DTORS_SECTION_FUNCTION
|
|||
switch (GET_CODE (addr)) \
|
||||
{ \
|
||||
case REG: \
|
||||
fprintf (FILE, "0(0,%s)", reg_names [REGNO (addr)]); \
|
||||
fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
|
||||
break; \
|
||||
case PLUS: \
|
||||
if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
|
||||
|
@ -2438,7 +2438,7 @@ DTORS_SECTION_FUNCTION
|
|||
offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); \
|
||||
else \
|
||||
abort (); \
|
||||
fprintf (FILE, "%d(0,%s)", offset, reg_names [REGNO (base)]); \
|
||||
fprintf (FILE, "%d(%s)", offset, reg_names [REGNO (base)]); \
|
||||
break; \
|
||||
case LO_SUM: \
|
||||
if (!symbolic_operand (XEXP (addr, 1))) \
|
||||
|
@ -2455,7 +2455,7 @@ DTORS_SECTION_FUNCTION
|
|||
fputs (")", FILE); \
|
||||
break; \
|
||||
case CONST_INT: \
|
||||
fprintf (FILE, "%d(0,0)", INTVAL (addr)); \
|
||||
fprintf (FILE, "%d(%r0)", INTVAL (addr)); \
|
||||
break; \
|
||||
default: \
|
||||
output_addr_const (FILE, addr); \
|
||||
|
|
|
@ -1450,9 +1450,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"ldwx %1(0,%2),%0\";
|
||||
return \"ldwx %1(%2),%0\";
|
||||
else
|
||||
return \"ldwx %2(0,%1),%0\";
|
||||
return \"ldwx %2(%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -1469,9 +1469,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[1] == hard_frame_pointer_rtx
|
||||
|| operands[1] == stack_pointer_rtx)
|
||||
return \"ldwx %2(0,%1),%0\";
|
||||
return \"ldwx %2(%1),%0\";
|
||||
else
|
||||
return \"ldwx %1(0,%2),%0\";
|
||||
return \"ldwx %1(%2),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -1488,8 +1488,8 @@
|
|||
"*
|
||||
{
|
||||
if (INTVAL (operands[2]) < 0)
|
||||
return \"ldwm %2(0,%1),%0\";
|
||||
return \"ldws,mb %2(0,%1),%0\";
|
||||
return \"ldwm %2(%1),%0\";
|
||||
return \"ldws,mb %2(%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -1504,8 +1504,8 @@
|
|||
"*
|
||||
{
|
||||
if (INTVAL (operands[1]) < 0)
|
||||
return \"stwm %r2,%1(0,%0)\";
|
||||
return \"stws,mb %r2,%1(0,%0)\";
|
||||
return \"stwm %r2,%1(%0)\";
|
||||
return \"stws,mb %r2,%1(%0)\";
|
||||
}"
|
||||
[(set_attr "type" "store")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -1520,8 +1520,8 @@
|
|||
"*
|
||||
{
|
||||
if (INTVAL (operands[2]) > 0)
|
||||
return \"ldwm %2(0,%1),%0\";
|
||||
return \"ldws,ma %2(0,%1),%0\";
|
||||
return \"ldwm %2(%1),%0\";
|
||||
return \"ldws,ma %2(%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -1536,8 +1536,8 @@
|
|||
"*
|
||||
{
|
||||
if (INTVAL (operands[2]) > 0)
|
||||
return \"stwm %r1,%2(0,%0)\";
|
||||
return \"stws,ma %r1,%2(0,%0)\";
|
||||
return \"stwm %r1,%2(%0)\";
|
||||
return \"stws,ma %r1,%2(%0)\";
|
||||
}"
|
||||
[(set_attr "type" "store")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -1785,9 +1785,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"ldhx %1(0,%2),%0\";
|
||||
return \"ldhx %1(%2),%0\";
|
||||
else
|
||||
return \"ldhx %2(0,%1),%0\";
|
||||
return \"ldhx %2(%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -1804,9 +1804,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[1] == hard_frame_pointer_rtx
|
||||
|| operands[1] == stack_pointer_rtx)
|
||||
return \"ldhx %2(0,%1),%0\";
|
||||
return \"ldhx %2(%1),%0\";
|
||||
else
|
||||
return \"ldhx %1(0,%2),%0\";
|
||||
return \"ldhx %1(%2),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -1826,9 +1826,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"ldhx %1(0,%2),%0\";
|
||||
return \"ldhx %1(%2),%0\";
|
||||
else
|
||||
return \"ldhx %2(0,%1),%0\";
|
||||
return \"ldhx %2(%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -1847,9 +1847,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[1] == hard_frame_pointer_rtx
|
||||
|| operands[1] == stack_pointer_rtx)
|
||||
return \"ldhx %2(0,%1),%0\";
|
||||
return \"ldhx %2(%1),%0\";
|
||||
else
|
||||
return \"ldhx %1(0,%2),%0\";
|
||||
return \"ldhx %1(%2),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -1861,7 +1861,7 @@
|
|||
(set (match_dup 1)
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
""
|
||||
"ldhs,mb %2(0,%1),%0"
|
||||
"ldhs,mb %2(%1),%0"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
|
@ -1875,7 +1875,7 @@
|
|||
(set (match_dup 1)
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
""
|
||||
"ldhs,mb %2(0,%1),%0"
|
||||
"ldhs,mb %2(%1),%0"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
|
@ -1886,7 +1886,7 @@
|
|||
(set (match_dup 0)
|
||||
(plus:SI (match_dup 0) (match_dup 1)))]
|
||||
""
|
||||
"sths,mb %r2,%1(0,%0)"
|
||||
"sths,mb %r2,%1(%0)"
|
||||
[(set_attr "type" "store")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
|
@ -1947,9 +1947,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"ldbx %1(0,%2),%0\";
|
||||
return \"ldbx %1(%2),%0\";
|
||||
else
|
||||
return \"ldbx %2(0,%1),%0\";
|
||||
return \"ldbx %2(%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -1966,9 +1966,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[1] == hard_frame_pointer_rtx
|
||||
|| operands[1] == stack_pointer_rtx)
|
||||
return \"ldbx %2(0,%1),%0\";
|
||||
return \"ldbx %2(%1),%0\";
|
||||
else
|
||||
return \"ldbx %1(0,%2),%0\";
|
||||
return \"ldbx %1(%2),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -1988,9 +1988,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"ldbx %1(0,%2),%0\";
|
||||
return \"ldbx %1(%2),%0\";
|
||||
else
|
||||
return \"ldbx %2(0,%1),%0\";
|
||||
return \"ldbx %2(%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -2009,9 +2009,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[1] == hard_frame_pointer_rtx
|
||||
|| operands[1] == stack_pointer_rtx)
|
||||
return \"ldbx %2(0,%1),%0\";
|
||||
return \"ldbx %2(%1),%0\";
|
||||
else
|
||||
return \"ldbx %1(0,%2),%0\";
|
||||
return \"ldbx %1(%2),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -2030,9 +2030,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"ldbx %1(0,%2),%0\";
|
||||
return \"ldbx %1(%2),%0\";
|
||||
else
|
||||
return \"ldbx %2(0,%1),%0\";
|
||||
return \"ldbx %2(%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -2051,9 +2051,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[1] == hard_frame_pointer_rtx
|
||||
|| operands[1] == stack_pointer_rtx)
|
||||
return \"ldbx %2(0,%1),%0\";
|
||||
return \"ldbx %2(%1),%0\";
|
||||
else
|
||||
return \"ldbx %1(0,%2),%0\";
|
||||
return \"ldbx %1(%2),%0\";
|
||||
}"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -2064,7 +2064,7 @@
|
|||
(match_operand:SI 2 "int5_operand" "L"))))
|
||||
(set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
|
||||
""
|
||||
"ldbs,mb %2(0,%1),%0"
|
||||
"ldbs,mb %2(%1),%0"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
|
@ -2076,7 +2076,7 @@
|
|||
(match_operand:SI 2 "int5_operand" "L")))))
|
||||
(set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
|
||||
""
|
||||
"ldbs,mb %2(0,%1),%0"
|
||||
"ldbs,mb %2(%1),%0"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
|
@ -2087,7 +2087,7 @@
|
|||
(match_operand:SI 2 "int5_operand" "L")))))
|
||||
(set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
|
||||
""
|
||||
"ldbs,mb %2(0,%1),%0"
|
||||
"ldbs,mb %2(%1),%0"
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
|
@ -2098,7 +2098,7 @@
|
|||
(set (match_dup 0)
|
||||
(plus:SI (match_dup 0) (match_dup 1)))]
|
||||
""
|
||||
"stbs,mb %r2,%1(0,%0)"
|
||||
"stbs,mb %r2,%1(%0)"
|
||||
[(set_attr "type" "store")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
|
@ -2305,9 +2305,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"flddx %1(0,%2),%0\";
|
||||
return \"flddx %1(%2),%0\";
|
||||
else
|
||||
return \"flddx %2(0,%1),%0\";
|
||||
return \"flddx %2(%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -2324,9 +2324,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[1] == hard_frame_pointer_rtx
|
||||
|| operands[1] == stack_pointer_rtx)
|
||||
return \"flddx %2(0,%1),%0\";
|
||||
return \"flddx %2(%1),%0\";
|
||||
else
|
||||
return \"flddx %1(0,%2),%0\";
|
||||
return \"flddx %1(%2),%0\";
|
||||
}"
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -2343,9 +2343,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"fstdx %0,%1(0,%2)\";
|
||||
return \"fstdx %0,%1(%2)\";
|
||||
else
|
||||
return \"fstdx %0,%2(0,%1)\";
|
||||
return \"fstdx %0,%2(%1)\";
|
||||
}"
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -2362,9 +2362,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[1] == hard_frame_pointer_rtx
|
||||
|| operands[1] == stack_pointer_rtx)
|
||||
return \"fstdx %0,%2(0,%1)\";
|
||||
return \"fstdx %0,%2(%1)\";
|
||||
else
|
||||
return \"fstdx %0,%1(0,%2)\";
|
||||
return \"fstdx %0,%1(%2)\";
|
||||
}"
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -2610,9 +2610,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"fldwx %1(0,%2),%0\";
|
||||
return \"fldwx %1(%2),%0\";
|
||||
else
|
||||
return \"fldwx %2(0,%1),%0\";
|
||||
return \"fldwx %2(%1),%0\";
|
||||
}"
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -2629,9 +2629,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[1] == hard_frame_pointer_rtx
|
||||
|| operands[1] == stack_pointer_rtx)
|
||||
return \"fldwx %2(0,%1),%0\";
|
||||
return \"fldwx %2(%1),%0\";
|
||||
else
|
||||
return \"fldwx %1(0,%2),%0\";
|
||||
return \"fldwx %1(%2),%0\";
|
||||
}"
|
||||
[(set_attr "type" "fpload")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -2648,9 +2648,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[2] == hard_frame_pointer_rtx
|
||||
|| operands[2] == stack_pointer_rtx)
|
||||
return \"fstwx %0,%1(0,%2)\";
|
||||
return \"fstwx %0,%1(%2)\";
|
||||
else
|
||||
return \"fstwx %0,%2(0,%1)\";
|
||||
return \"fstwx %0,%2(%1)\";
|
||||
}"
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -2667,9 +2667,9 @@
|
|||
pseudos that don't get hard registers. Deal with it. */
|
||||
if (operands[1] == hard_frame_pointer_rtx
|
||||
|| operands[1] == stack_pointer_rtx)
|
||||
return \"fstwx %0,%2(0,%1)\";
|
||||
return \"fstwx %0,%2(%1)\";
|
||||
else
|
||||
return \"fstwx %0,%1(0,%2)\";
|
||||
return \"fstwx %0,%1(%2)\";
|
||||
}"
|
||||
[(set_attr "type" "fpstore")
|
||||
(set_attr "length" "4")])
|
||||
|
@ -5039,7 +5039,7 @@
|
|||
(use (mem:SI (match_operand:SI 0 "register_operand" "r")))
|
||||
(use (mem:SI (match_operand:SI 1 "register_operand" "r")))]
|
||||
""
|
||||
"fdc 0(0,%0)\;fdc 0(0,%1)\;sync"
|
||||
"fdc 0(%0)\;fdc 0(%1)\;sync"
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "length" "12")])
|
||||
|
||||
|
@ -5051,7 +5051,7 @@
|
|||
(clobber (match_operand:SI 3 "register_operand" "=&r"))
|
||||
(clobber (match_operand:SI 4 "register_operand" "=&r"))]
|
||||
""
|
||||
"mfsp %%sr0,%4\;ldsid (0,%2),%3\;mtsp %3,%%sr0\;fic 0(%%sr0,%0)\;fic 0(%%sr0,%1)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
|
||||
"mfsp %%sr0,%4\;ldsid (%2),%3\;mtsp %3,%%sr0\;fic 0(%%sr0,%0)\;fic 0(%%sr0,%1)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "length" "52")])
|
||||
|
||||
|
|
Loading…
Reference in New Issue