gcc/
* doc/md.texi (extv@var{m}, extvmisalign@var{m}, extzv@var{m})
(extzvmisalign@var{m}, insv@var{m}, insvmisalign@var{m}): Document.
(insv, extv, extzv): Deprecate.
* optabs.def (insv_optab, extv_optab, extzv_optab)
(insvmisalign_optab, extvmisalign_optab, extzvmisalign_optab):
New optabs.
* optabs.c (get_optab_extraction_insn): New function.
(get_extraction_insn): Use it.
* config/mips/mips.md (extv): Split into...
(extvmisalign<mode>, extv<mode>): ...these new patterns. Rename
existing extv<mode> pattern to...
(*extv<mode>): ...this.
(extzv): Split into...
(extzvmisalign<mode>, extzv<mode>): ...these new patterns. Rename
existing extzv<mode> pattern to...
(*extzv<mode>): ...this.
(insv): Split into...
(insvmisalign<mode>, insv<mode>): ...these new patterns. Rename
existing insv<mode> pattern to...
(*insv<mode>): ...this. Use const_int_operand rather than
immediate_operand.
* config/mips/mips.c (mips_block_move_straight): Use set_mem_size
to set the size of BLKmode accesses.
(mips_get_unaligned_mem): Require OP0 to be a BLKmode memory,
turning it from an "rtx *" to an rtx.
(mips_expand_ext_as_unaligned_load): Simplify for new optab
interface. Update call to mips_get_unaligned_mem.
(mips_expand_ins_as_unaligned_store): Update call to
mips_get_unaligned_mem.
From-SVN: r193606
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
fcdd52b73c
commit
d2eeb2d179
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@ -1,3 +1,35 @@
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2012-11-18 Richard Sandiford <rdsandiford@googlemail.com>
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* doc/md.texi (extv@var{m}, extvmisalign@var{m}, extzv@var{m})
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(extzvmisalign@var{m}, insv@var{m}, insvmisalign@var{m}): Document.
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(insv, extv, extzv): Deprecate.
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* optabs.def (insv_optab, extv_optab, extzv_optab)
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(insvmisalign_optab, extvmisalign_optab, extzvmisalign_optab):
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New optabs.
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* optabs.c (get_optab_extraction_insn): New function.
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(get_extraction_insn): Use it.
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* config/mips/mips.md (extv): Split into...
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(extvmisalign<mode>, extv<mode>): ...these new patterns. Rename
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existing extv<mode> pattern to...
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(*extv<mode>): ...this.
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(extzv): Split into...
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(extzvmisalign<mode>, extzv<mode>): ...these new patterns. Rename
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existing extzv<mode> pattern to...
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(*extzv<mode>): ...this.
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(insv): Split into...
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(insvmisalign<mode>, insv<mode>): ...these new patterns. Rename
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existing insv<mode> pattern to...
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(*insv<mode>): ...this. Use const_int_operand rather than
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immediate_operand.
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* config/mips/mips.c (mips_block_move_straight): Use set_mem_size
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to set the size of BLKmode accesses.
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(mips_get_unaligned_mem): Require OP0 to be a BLKmode memory,
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turning it from an "rtx *" to an rtx.
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(mips_expand_ext_as_unaligned_load): Simplify for new optab
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interface. Update call to mips_get_unaligned_mem.
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(mips_expand_ins_as_unaligned_store): Update call to
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mips_get_unaligned_mem.
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2012-11-18 Richard Sandiford <rdsandiford@googlemail.com>
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* Makefile.in (recog.o): Add insn-codes.h.
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@ -7096,6 +7096,7 @@ mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
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else
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{
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rtx part = adjust_address (src, BLKmode, offset);
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set_mem_size (part, delta);
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if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
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gcc_unreachable ();
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}
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@ -7108,6 +7109,7 @@ mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
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else
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{
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rtx part = adjust_address (dest, BLKmode, offset);
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set_mem_size (part, delta);
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if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
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gcc_unreachable ();
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}
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@ -7359,10 +7361,8 @@ mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
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}
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/* Return true if it is possible to use left/right accesses for a
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bitfield of WIDTH bits starting BITPOS bits into *OP. When
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returning true, update *OP, *LEFT and *RIGHT as follows:
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*OP is a BLKmode reference to the whole field.
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bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
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When returning true, update *LEFT and *RIGHT as follows:
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*LEFT is a QImode reference to the first byte if big endian or
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the last byte if little endian. This address can be used in the
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@ -7372,16 +7372,11 @@ mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
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can be used in the patterning right-side instruction. */
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static bool
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mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
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mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
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rtx *left, rtx *right)
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{
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rtx first, last;
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/* Check that the operand really is a MEM. Not all the extv and
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extzv predicates are checked. */
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if (!MEM_P (*op))
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return false;
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/* Check that the size is valid. */
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if (width != 32 && (!TARGET_64BIT || width != 64))
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return false;
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@ -7394,20 +7389,12 @@ mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
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/* Reject aligned bitfields: we want to use a normal load or store
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instead of a left/right pair. */
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if (MEM_ALIGN (*op) >= width)
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if (MEM_ALIGN (op) >= width)
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return false;
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/* Create a copy of *OP that refers to the whole field. This also has
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the effect of legitimizing *OP's address for BLKmode, possibly
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simplifying it. */
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*op = copy_rtx (adjust_address (*op, BLKmode, 0));
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set_mem_size (*op, width / BITS_PER_UNIT);
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/* Get references to both ends of the field. We deliberately don't
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use the original QImode *OP for FIRST since the new BLKmode one
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might have a simpler address. */
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first = adjust_address (*op, QImode, 0);
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last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
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/* Get references to both ends of the field. */
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first = adjust_address (op, QImode, 0);
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last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
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/* Allocate to LEFT and RIGHT according to endianness. LEFT should
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correspond to the MSB and RIGHT to the LSB. */
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@ -7434,14 +7421,6 @@ mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
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rtx left, right, temp;
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rtx dest1 = NULL_RTX;
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/* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
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be a paradoxical word_mode subreg. This is the only case in which
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we allow the destination to be larger than the source. */
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if (GET_CODE (dest) == SUBREG
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&& GET_MODE (dest) == DImode
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&& GET_MODE (SUBREG_REG (dest)) == SImode)
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dest = SUBREG_REG (dest);
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/* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
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be a DImode, create a new temp and emit a zero extend at the end. */
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if (GET_MODE (dest) == DImode
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@ -7452,12 +7431,7 @@ mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
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dest = gen_reg_rtx (SImode);
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}
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/* After the above adjustment, the destination must be the same
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width as the source. */
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if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
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return false;
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if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
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if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
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return false;
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temp = gen_reg_rtx (GET_MODE (dest));
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@ -7499,7 +7473,7 @@ mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
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rtx left, right;
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enum machine_mode mode;
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if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
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if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
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return false;
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mode = mode_for_size (width, MODE_INT, 0);
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@ -3777,11 +3777,11 @@
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;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
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(define_expand "extv"
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[(set (match_operand 0 "register_operand")
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(sign_extract (match_operand 1 "nonimmediate_operand")
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(match_operand 2 "const_int_operand")
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(match_operand 3 "const_int_operand")))]
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(define_expand "extvmisalign<mode>"
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[(set (match_operand:GPR 0 "register_operand")
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(sign_extract:GPR (match_operand:BLK 1 "memory_operand")
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(match_operand 2 "const_int_operand")
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(match_operand 3 "const_int_operand")))]
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"!TARGET_MIPS16"
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{
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if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
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@ -3789,22 +3789,22 @@
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INTVAL (operands[3]),
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/*unsigned=*/ false))
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DONE;
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else if (register_operand (operands[1], GET_MODE (operands[0]))
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&& ISA_HAS_EXTS && UINTVAL (operands[2]) <= 32)
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{
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if (GET_MODE (operands[0]) == DImode)
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emit_insn (gen_extvdi (operands[0], operands[1], operands[2],
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operands[3]));
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else
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emit_insn (gen_extvsi (operands[0], operands[1], operands[2],
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operands[3]));
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DONE;
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}
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else
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FAIL;
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})
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(define_insn "extv<mode>"
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(define_expand "extv<mode>"
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[(set (match_operand:GPR 0 "register_operand")
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(sign_extract:GPR (match_operand:GPR 1 "register_operand")
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(match_operand 2 "const_int_operand")
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(match_operand 3 "const_int_operand")))]
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"ISA_HAS_EXTS"
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{
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if (UINTVAL (operands[2]) > 32)
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FAIL;
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})
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(define_insn "*extv<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(sign_extract:GPR (match_operand:GPR 1 "register_operand" "d")
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(match_operand 2 "const_int_operand" "")
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@ -3814,35 +3814,35 @@
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[(set_attr "type" "arith")
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(set_attr "mode" "<MODE>")])
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(define_expand "extzv"
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[(set (match_operand 0 "register_operand")
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(zero_extract (match_operand 1 "nonimmediate_operand")
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(match_operand 2 "const_int_operand")
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(match_operand 3 "const_int_operand")))]
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(define_expand "extzvmisalign<mode>"
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[(set (match_operand:GPR 0 "register_operand")
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(zero_extract:GPR (match_operand:BLK 1 "memory_operand")
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(match_operand 2 "const_int_operand")
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(match_operand 3 "const_int_operand")))]
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"!TARGET_MIPS16"
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{
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if (mips_expand_ext_as_unaligned_load (operands[0], operands[1],
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INTVAL (operands[2]),
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INTVAL (operands[3]),
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/*unsigned=*/true))
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/*unsigned=*/ true))
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DONE;
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else if (mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
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INTVAL (operands[3])))
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{
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if (GET_MODE (operands[0]) == DImode)
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emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
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operands[3]));
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else
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emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
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operands[3]));
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DONE;
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}
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else
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FAIL;
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})
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(define_insn "extzv<mode>"
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(define_expand "extzv<mode>"
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[(set (match_operand:GPR 0 "register_operand")
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(zero_extract:GPR (match_operand:GPR 1 "register_operand")
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(match_operand 2 "const_int_operand")
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(match_operand 3 "const_int_operand")))]
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""
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{
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if (!mips_use_ins_ext_p (operands[1], INTVAL (operands[2]),
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INTVAL (operands[3])))
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FAIL;
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})
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(define_insn "*extzv<mode>"
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[(set (match_operand:GPR 0 "register_operand" "=d")
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(zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
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(match_operand 2 "const_int_operand" "")
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@ -3865,36 +3865,37 @@
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(set_attr "mode" "SI")])
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(define_expand "insv"
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[(set (zero_extract (match_operand 0 "nonimmediate_operand")
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(match_operand 1 "immediate_operand")
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(match_operand 2 "immediate_operand"))
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(match_operand 3 "reg_or_0_operand"))]
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(define_expand "insvmisalign<mode>"
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[(set (zero_extract:GPR (match_operand:BLK 0 "memory_operand")
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(match_operand 1 "const_int_operand")
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(match_operand 2 "const_int_operand"))
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(match_operand:GPR 3 "reg_or_0_operand"))]
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"!TARGET_MIPS16"
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{
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if (mips_expand_ins_as_unaligned_store (operands[0], operands[3],
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INTVAL (operands[1]),
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INTVAL (operands[2])))
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DONE;
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else if (mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
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INTVAL (operands[2])))
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{
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if (GET_MODE (operands[0]) == DImode)
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emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
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operands[3]));
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else
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emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
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operands[3]));
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DONE;
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}
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else
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FAIL;
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else
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FAIL;
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})
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(define_insn "insv<mode>"
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(define_expand "insv<mode>"
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[(set (zero_extract:GPR (match_operand:GPR 0 "register_operand")
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(match_operand 1 "const_int_operand")
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(match_operand 2 "const_int_operand"))
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(match_operand:GPR 3 "reg_or_0_operand"))]
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""
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{
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if (!mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
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INTVAL (operands[2])))
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FAIL;
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})
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(define_insn "*insv<mode>"
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[(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
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(match_operand:SI 1 "immediate_operand" "I")
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(match_operand:SI 2 "immediate_operand" "I"))
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(match_operand:SI 1 "const_int_operand" "")
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(match_operand:SI 2 "const_int_operand" ""))
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(match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
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"mips_use_ins_ext_p (operands[0], INTVAL (operands[1]),
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INTVAL (operands[2]))"
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@ -5294,6 +5294,62 @@ Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
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When overflows or underflows happen, the instruction saturates the
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results to the maximum or the minimum.
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@cindex @code{extv@var{m}} instruction pattern
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@item @samp{extv@var{m}}
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Extract a bit-field from register operand 1, sign-extend it, and store
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it in operand 0. Operand 2 specifies the width of the field in bits
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and operand 3 the starting bit, which counts from the most significant
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bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit
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otherwise.
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Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a
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target-specific mode.
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@cindex @code{extvmisalign@var{m}} instruction pattern
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@item @samp{extvmisalign@var{m}}
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Extract a bit-field from memory operand 1, sign extend it, and store
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it in operand 0. Operand 2 specifies the width in bits and operand 3
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the starting bit. The starting bit is always somewhere in the first byte of
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operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
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is true and from the least significant bit otherwise.
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Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode.
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Operands 2 and 3 have a target-specific mode.
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The instruction must not read beyond the last byte of the bit-field.
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@cindex @code{extzv@var{m}} instruction pattern
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@item @samp{extzv@var{m}}
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Like @samp{extv@var{m}} except that the bit-field value is zero-extended.
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@cindex @code{extzvmisalign@var{m}} instruction pattern
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@item @samp{extzvmisalign@var{m}}
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Like @samp{extvmisalign@var{m}} except that the bit-field value is
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zero-extended.
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@cindex @code{insv@var{m}} instruction pattern
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@item @samp{insv@var{m}}
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Insert operand 3 into a bit-field of register operand 0. Operand 1
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specifies the width of the field in bits and operand 2 the starting bit,
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which counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
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is true and from the least significant bit otherwise.
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Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a
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target-specific mode.
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|
||||
@cindex @code{insvmisalign@var{m}} instruction pattern
|
||||
@item @samp{insvmisalign@var{m}}
|
||||
Insert operand 3 into a bit-field of memory operand 0. Operand 1
|
||||
specifies the width of the field in bits and operand 2 the starting bit.
|
||||
The starting bit is always somewhere in the first byte of operand 0;
|
||||
it counts from the most significant bit if @samp{BITS_BIG_ENDIAN}
|
||||
is true and from the least significant bit otherwise.
|
||||
|
||||
Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode.
|
||||
Operands 1 and 2 have a target-specific mode.
|
||||
|
||||
The instruction must not read or write beyond the last byte of the bit-field.
|
||||
|
||||
@cindex @code{extv} instruction pattern
|
||||
@item @samp{extv}
|
||||
Extract a bit-field from operand 1 (a register or memory operand), where
|
||||
|
|
@ -5309,10 +5365,16 @@ for operands 2 and 3 and the constant is never zero for operand 2.
|
|||
The bit-field value is sign-extended to a full word integer
|
||||
before it is stored in operand 0.
|
||||
|
||||
This pattern is deprecated; please use @samp{extv@var{m}} and
|
||||
@code{extvmisalign@var{m}} instead.
|
||||
|
||||
@cindex @code{extzv} instruction pattern
|
||||
@item @samp{extzv}
|
||||
Like @samp{extv} except that the bit-field value is zero-extended.
|
||||
|
||||
This pattern is deprecated; please use @samp{extzv@var{m}} and
|
||||
@code{extzvmisalign@var{m}} instead.
|
||||
|
||||
@cindex @code{insv} instruction pattern
|
||||
@item @samp{insv}
|
||||
Store operand 3 (which must be valid for @code{word_mode}) into a
|
||||
|
|
@ -5324,6 +5386,9 @@ Operands 1 and 2 must be valid for @code{word_mode}.
|
|||
The RTL generation pass generates this instruction only with constants
|
||||
for operands 1 and 2 and the constant is never zero for operand 1.
|
||||
|
||||
This pattern is deprecated; please use @samp{insv@var{m}} and
|
||||
@code{insvmisalign@var{m}} instead.
|
||||
|
||||
@cindex @code{mov@var{mode}cc} instruction pattern
|
||||
@item @samp{mov@var{mode}cc}
|
||||
Conditionally move operand 2 or operand 3 into operand 0 according to the
|
||||
|
|
|
|||
38
gcc/optabs.c
38
gcc/optabs.c
|
|
@ -8294,6 +8294,35 @@ get_traditional_extraction_insn (extraction_insn *insn,
|
|||
return true;
|
||||
}
|
||||
|
||||
/* Return true if an optab exists to perform an insertion or extraction
|
||||
of type TYPE in mode MODE. Describe the instruction in *INSN if so.
|
||||
|
||||
REG_OPTAB is the optab to use for register structures and
|
||||
MISALIGN_OPTAB is the optab to use for misaligned memory structures.
|
||||
POS_OP is the operand number of the bit position. */
|
||||
|
||||
static bool
|
||||
get_optab_extraction_insn (struct extraction_insn *insn,
|
||||
enum extraction_type type,
|
||||
enum machine_mode mode, direct_optab reg_optab,
|
||||
direct_optab misalign_optab, int pos_op)
|
||||
{
|
||||
direct_optab optab = (type == ET_unaligned_mem ? misalign_optab : reg_optab);
|
||||
enum insn_code icode = direct_optab_handler (optab, mode);
|
||||
if (icode == CODE_FOR_nothing)
|
||||
return false;
|
||||
|
||||
const struct insn_data_d *data = &insn_data[icode];
|
||||
|
||||
insn->icode = icode;
|
||||
insn->field_mode = mode;
|
||||
insn->struct_mode = (type == ET_unaligned_mem ? BLKmode : mode);
|
||||
insn->pos_mode = data->operand[pos_op].mode;
|
||||
if (insn->pos_mode == VOIDmode)
|
||||
insn->pos_mode = word_mode;
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Return true if an instruction exists to perform an insertion or
|
||||
extraction (PATTERN says which) of type TYPE in mode MODE.
|
||||
Describe the instruction in *INSN if so. */
|
||||
|
|
@ -8311,21 +8340,24 @@ get_extraction_insn (extraction_insn *insn,
|
|||
&& get_traditional_extraction_insn (insn, type, mode,
|
||||
CODE_FOR_insv, 0, 3))
|
||||
return true;
|
||||
return false;
|
||||
return get_optab_extraction_insn (insn, type, mode, insv_optab,
|
||||
insvmisalign_optab, 2);
|
||||
|
||||
case EP_extv:
|
||||
if (HAVE_extv
|
||||
&& get_traditional_extraction_insn (insn, type, mode,
|
||||
CODE_FOR_extv, 1, 0))
|
||||
return true;
|
||||
return false;
|
||||
return get_optab_extraction_insn (insn, type, mode, extv_optab,
|
||||
extvmisalign_optab, 3);
|
||||
|
||||
case EP_extzv:
|
||||
if (HAVE_extzv
|
||||
&& get_traditional_extraction_insn (insn, type, mode,
|
||||
CODE_FOR_extzv, 1, 0))
|
||||
return true;
|
||||
return false;
|
||||
return get_optab_extraction_insn (insn, type, mode, extzv_optab,
|
||||
extzvmisalign_optab, 3);
|
||||
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
|
|
|
|||
|
|
@ -171,6 +171,12 @@ OPTAB_DC(mov_optab, "mov$a", SET)
|
|||
OPTAB_DC(movstrict_optab, "movstrict$a", STRICT_LOW_PART)
|
||||
OPTAB_D (movmisalign_optab, "movmisalign$a")
|
||||
OPTAB_D (storent_optab, "storent$a")
|
||||
OPTAB_D (insv_optab, "insv$a")
|
||||
OPTAB_D (extv_optab, "extv$a")
|
||||
OPTAB_D (extzv_optab, "extzv$a")
|
||||
OPTAB_D (insvmisalign_optab, "insvmisalign$a")
|
||||
OPTAB_D (extvmisalign_optab, "extvmisalign$a")
|
||||
OPTAB_D (extzvmisalign_optab, "extzvmisalign$a")
|
||||
OPTAB_D (push_optab, "push$a1")
|
||||
OPTAB_D (reload_in_optab, "reload_in$a")
|
||||
OPTAB_D (reload_out_optab, "reload_out$a")
|
||||
|
|
|
|||
Loading…
Reference in New Issue