re PR target/19235 (GCC generates SSE2 instructions for AthlonXP which doesn't support them.)
PR target/19235
* config/i386/i386.md (movdi_2): Separate SSE1 and SSE2 alternatives.
(mov<MMXMODEI>_internal): Likewise.
(movdf_nointeger): Prefer Y while not preferring, but allowing, x.
Add V2SF case; use it for SSE1; don't use TI.
(movdf_integer): Likewise.
(mov<SSEMODEI>_internal, movti_internal): Force V4SF for SSE1.
From-SVN: r92889
This commit is contained in:
Richard Henderson
Richard Henderson
parent
7d23434bbe
commit
d30c94610f
@ -1,3 +1,13 @@
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2005-01-03 Richard Henderson <rth@redhat.com>
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PR target/19235
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* config/i386/i386.md (movdi_2): Separate SSE1 and SSE2 alternatives.
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(mov<MMXMODEI>_internal): Likewise.
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(movdf_nointeger): Prefer Y while not preferring, but allowing, x.
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Add V2SF case; use it for SSE1; don't use TI.
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(movdf_integer): Likewise.
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(mov<SSEMODEI>_internal, movti_internal): Force V4SF for SSE1.
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2005-01-03 Ira Rosen <irar@il.ibm.com>
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* tree-vectorizer.c (vect_strip_conversions): New function.
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@ -1899,8 +1899,10 @@
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(set_attr "length_immediate" "1")])
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(define_insn "*movdi_2"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!m*y,!*y,!m,!*x,!*x")
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(match_operand:DI 1 "general_operand" "riFo,riF,*y,m,*x,*x,m"))]
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=r ,o ,m*y,*y,m ,*Y,*Y,m ,*x,*x")
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(match_operand:DI 1 "general_operand"
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"riFo,riF,*y ,m ,*Y,*Y,m ,*x,*x,m "))]
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"!TARGET_64BIT
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&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
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"@
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@ -1910,9 +1912,12 @@
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movq\t{%1, %0|%0, %1}
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movq\t{%1, %0|%0, %1}
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movdqa\t{%1, %0|%0, %1}
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movq\t{%1, %0|%0, %1}"
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[(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
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(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
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movq\t{%1, %0|%0, %1}
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movlps\t{%1, %0|%0, %1}
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movaps\t{%1, %0|%0, %1}
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movlps\t{%1, %0|%0, %1}"
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[(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov,ssemov,ssemov,ssemov")
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(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,V2SF,V4SF,V2SF")])
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(define_split
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[(set (match_operand:DI 0 "push_operand" "")
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@ -2444,9 +2449,9 @@
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(define_insn "*movdf_nointeger"
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[(set (match_operand:DF 0 "nonimmediate_operand"
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"=f#x,m ,f#x,*r ,o ,x#f,x#f,x#f ,m")
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"=f#Y,m ,f#Y,*r ,o ,Y#f*x,Y#f*x,Y#f*x ,m ")
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(match_operand:DF 1 "general_operand"
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"fm#x,f#x,G ,*roF,F*r,C ,x#f,xHm#f,x#f"))]
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"fm#Y,f#Y,G ,*roF,F*r,C ,Y#f*x,HmY#f*x,Y#f*x"))]
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"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
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&& ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
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&& (reload_in_progress || reload_completed
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@ -2500,6 +2505,8 @@
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return "movsd\t{%1, %0|%0, %1}";
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case MODE_V1DF:
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return "movlpd\t{%1, %0|%0, %1}";
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case MODE_V2SF:
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return "movlps\t{%1, %0|%0, %1}";
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default:
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abort ();
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}
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@ -2510,18 +2517,17 @@
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}
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[(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
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(set (attr "mode")
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(cond [(eq_attr "alternative" "3,4")
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(cond [(eq_attr "alternative" "0,1,2")
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(const_string "DF")
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(eq_attr "alternative" "3,4")
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(const_string "SI")
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/* For SSE1, we have many fewer alternatives. */
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(eq (symbol_ref "TARGET_SSE2") (const_int 0))
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(cond [(eq_attr "alternative" "5,6")
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(if_then_else
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(ne (symbol_ref "optimize_size") (const_int 0))
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(const_string "V4SF")
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(const_string "TI"))
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(const_string "V4SF")
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]
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(const_string "DI"))
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(const_string "V2SF"))
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/* xorps is one byte shorter. */
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(eq_attr "alternative" "5")
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@ -2563,9 +2569,9 @@
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(define_insn "*movdf_integer"
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[(set (match_operand:DF 0 "nonimmediate_operand"
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"=f#Yr,m ,f#Yr,r#Yf ,o ,Y#rf,Y#rf,Y#rf ,m")
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"=f#Yr,m ,f#Yr,r#Yf ,o ,Y#rf*x,Y#rf*x,Y#rf*x,m")
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(match_operand:DF 1 "general_operand"
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"fm#Yr,f#Yr,G ,roF#Yf,Fr#Yf,C ,Y#rf,Ym#rf,Y#rf"))]
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"fm#Yr,f#Yr,G ,roF#Yf,Fr#Yf,C ,Y#rf*x,m ,Y#rf*x"))]
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"(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
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&& ((!optimize_size && TARGET_INTEGER_DFMODE_MOVES) || TARGET_64BIT)
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&& (reload_in_progress || reload_completed
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@ -2620,6 +2626,8 @@
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return "movsd\t{%1, %0|%0, %1}";
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case MODE_V1DF:
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return "movlpd\t{%1, %0|%0, %1}";
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case MODE_V2SF:
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return "movlps\t{%1, %0|%0, %1}";
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default:
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abort ();
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}
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@ -2630,18 +2638,17 @@
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}
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[(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
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(set (attr "mode")
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(cond [(eq_attr "alternative" "3,4")
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(cond [(eq_attr "alternative" "0,1,2")
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(const_string "DF")
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(eq_attr "alternative" "3,4")
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(const_string "SI")
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/* For SSE1, we have many fewer alternatives. */
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(eq (symbol_ref "TARGET_SSE2") (const_int 0))
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(cond [(eq_attr "alternative" "5,6")
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(if_then_else
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(ne (symbol_ref "optimize_size") (const_int 0))
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(const_string "V4SF")
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(const_string "TI"))
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(const_string "V4SF")
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]
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(const_string "DI"))
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(const_string "V2SF"))
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/* xorps is one byte shorter. */
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(eq_attr "alternative" "5")
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@ -19825,7 +19832,10 @@
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}
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[(set_attr "type" "ssemov")
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(set (attr "mode")
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(cond [(eq_attr "alternative" "0,1")
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(cond [(eq (symbol_ref "TARGET_SSE2") (const_int 0))
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(const_string "V4SF")
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(eq_attr "alternative" "0,1")
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(if_then_else
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(ne (symbol_ref "optimize_size")
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(const_int 0))
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@ -19878,9 +19888,9 @@
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(define_insn "*mov<mode>_internal"
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[(set (match_operand:MMXMODEI 0 "nonimmediate_operand"
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"=*y,*y ,m ,*y,*Y,*x,*x ,m")
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"=*y,*y ,m ,*y,*Y,*Y,*Y ,m ,*x,*x,*x,m")
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(match_operand:MMXMODEI 1 "vector_move_operand"
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"C ,*ym,*y,*Y,*y,C ,*xm,*x"))]
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"C ,*ym,*y,*Y,*y,C ,*Ym,*Y,C ,*x,m ,*x"))]
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"TARGET_MMX
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&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
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"@
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@ -19891,9 +19901,13 @@
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movq2dq\t{%1, %0|%0, %1}
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pxor\t%0, %0
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movq\t{%1, %0|%0, %1}
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movq\t{%1, %0|%0, %1}"
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[(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov")
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(set_attr "mode" "DI")])
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movq\t{%1, %0|%0, %1}
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xorps\t%0, %0
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movaps\t{%1, %0|%0, %1}
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movlps\t{%1, %0|%0, %1}
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movlps\t{%1, %0|%0, %1}"
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[(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov,ssemov,ssemov,ssemov,ssemov")
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(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF")])
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(define_expand "movv2sf"
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[(set (match_operand:V2SF 0 "nonimmediate_operand" "")
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@ -19983,7 +19997,10 @@
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}
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[(set_attr "type" "ssemov,ssemov,ssemov")
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(set (attr "mode")
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(cond [(eq_attr "alternative" "0,1")
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(cond [(eq (symbol_ref "TARGET_SSE2") (const_int 0))
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(const_string "V4SF")
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(eq_attr "alternative" "0,1")
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(if_then_else
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(ne (symbol_ref "optimize_size")
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(const_int 0))
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