mips.c (mips_reg_names): Change hilo entry to "".
* config/mips/mips.c (mips_reg_names): Change hilo entry to "". (mips_sw_reg_names): Likewise. (mips_regno_to_class): Change hilo entry to NO_REGS. (hilo_operand): Use MD_REG_P. (extend_operator): New predicate. (override_options): Remove 'a' constraint. (mips_secondary_reload_class): Remove hilo handling. Also remove handling of (plus sp reg) reloads for mips16. (mips_register_move_cost): Remove hilo handling. * config/mips/mips.h (FIXED_REGISTERS): Make hilo entry fixed. (MD_REG_LAST): Remove hilo from range. (HILO_REGNUM): Delete. (reg_class): Remove HILO_REG and HILO_AND_GR_REGS. (REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly. (PREDICATE_CODES): Add entry for extend_operator. (DEBUG_REGISTER_NAMES): Change hilo entry to "". * config/mips/mips.md: Remove hilo clobbers wherever they occur. Remove constraints from multiplication define_expands. Remove clobbers from "decorative" define_expand patterns. (UNSPEC_HILO_DELAY): Delete. (*mul_acc_si, *mul_sub_si): Add early-clobber to operand 6. (mulsidi3, umulsidi3): Change pattern to match the TARGET_64BIT case. Adjust C code to just emit insns for !TARGET_64BIT. (mulsidi3_internal): Rename to mulsidi3_32bit. (mulsidi3_64bit): Use a "d" constraint for the destination. Use extend_operator so that the pattern can handle umulsidi3 as well. Split the instruction after reload. (*mulsidi3_64bit_parts): New pattern, generated by mulsidi3_64bit. (umulsidi3_internal): Rename to umulsidi3_32bit. (umulsidi3_64bit): Remove. (*smsac_di, *umsac_di): Line-wrap fixes. (udivsi3_internal): Don't allow operand 2 to be constant. (udivdi3_internal, umodsi3_internal, umoddi3_internal): Likewise. (movdi_internal2, movsi_internal): Remove hilo alternatives. (reload_in[sd]i, reload_out[sd]i, hilo_delay): Remove. From-SVN: r67654
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
20db0e3c83
commit
d334c3c18f
@ -1,3 +1,41 @@
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2003-06-09 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.c (mips_reg_names): Change hilo entry to "".
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(mips_sw_reg_names): Likewise.
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(mips_regno_to_class): Change hilo entry to NO_REGS.
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(hilo_operand): Use MD_REG_P.
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(extend_operator): New predicate.
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(override_options): Remove 'a' constraint.
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(mips_secondary_reload_class): Remove hilo handling. Also remove
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handling of (plus sp reg) reloads for mips16.
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(mips_register_move_cost): Remove hilo handling.
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* config/mips/mips.h (FIXED_REGISTERS): Make hilo entry fixed.
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(MD_REG_LAST): Remove hilo from range.
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(HILO_REGNUM): Delete.
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(reg_class): Remove HILO_REG and HILO_AND_GR_REGS.
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(REG_CLASS_NAMES, REG_CLASS_CONTENTS): Update accordingly.
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(PREDICATE_CODES): Add entry for extend_operator.
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(DEBUG_REGISTER_NAMES): Change hilo entry to "".
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* config/mips/mips.md: Remove hilo clobbers wherever they occur.
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Remove constraints from multiplication define_expands. Remove
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clobbers from "decorative" define_expand patterns.
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(UNSPEC_HILO_DELAY): Delete.
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(*mul_acc_si, *mul_sub_si): Add early-clobber to operand 6.
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(mulsidi3, umulsidi3): Change pattern to match the TARGET_64BIT case.
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Adjust C code to just emit insns for !TARGET_64BIT.
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(mulsidi3_internal): Rename to mulsidi3_32bit.
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(mulsidi3_64bit): Use a "d" constraint for the destination.
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Use extend_operator so that the pattern can handle umulsidi3 as well.
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Split the instruction after reload.
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(*mulsidi3_64bit_parts): New pattern, generated by mulsidi3_64bit.
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(umulsidi3_internal): Rename to umulsidi3_32bit.
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(umulsidi3_64bit): Remove.
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(*smsac_di, *umsac_di): Line-wrap fixes.
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(udivsi3_internal): Don't allow operand 2 to be constant.
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(udivdi3_internal, umodsi3_internal, umoddi3_internal): Likewise.
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(movdi_internal2, movsi_internal): Remove hilo alternatives.
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(reload_in[sd]i, reload_out[sd]i, hilo_delay): Remove.
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2003-06-09 Richard Sandiford <rsandifo@redhat.com>
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PR target/10913
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@ -592,7 +592,7 @@ char mips_reg_names[][8] =
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"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
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"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
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"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
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"hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
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"hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
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"$fcc5","$fcc6","$fcc7","", "", "", "", "",
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"$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
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"$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
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@ -621,7 +621,7 @@ char mips_sw_reg_names[][8] =
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"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
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"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
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"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
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"hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
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"hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
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"$fcc5","$fcc6","$fcc7","$rap", "", "", "", "",
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"$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",
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"$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",
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@ -656,7 +656,7 @@ const enum reg_class mips_regno_to_class[] =
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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FP_REGS, FP_REGS, FP_REGS, FP_REGS,
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HI_REG, LO_REG, HILO_REG, ST_REGS,
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HI_REG, LO_REG, NO_REGS, ST_REGS,
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ST_REGS, ST_REGS, ST_REGS, ST_REGS,
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ST_REGS, ST_REGS, ST_REGS, NO_REGS,
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NO_REGS, NO_REGS, NO_REGS, NO_REGS,
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@ -1518,8 +1518,18 @@ hilo_operand (op, mode)
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enum machine_mode mode;
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{
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return ((mode == VOIDmode || mode == GET_MODE (op))
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&& REG_P (op)
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&& (REGNO (op) == HI_REGNUM || REGNO (op) == LO_REGNUM));
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&& REG_P (op) && MD_REG_P (REGNO (op)));
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}
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/* Return true if OP is an extension operator. */
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int
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extend_operator (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return ((mode == VOIDmode || mode == GET_MODE (op))
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&& (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND));
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}
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/* Return nonzero if the code of this rtx pattern is EQ or NE. */
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@ -5555,7 +5565,6 @@ override_options ()
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mips_char_to_class['f'] = (TARGET_HARD_FLOAT ? FP_REGS : NO_REGS);
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mips_char_to_class['h'] = HI_REG;
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mips_char_to_class['l'] = LO_REG;
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mips_char_to_class['a'] = HILO_REG;
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mips_char_to_class['x'] = MD_REGS;
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mips_char_to_class['b'] = ALL_REGS;
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mips_char_to_class['c'] = (TARGET_ABICALLS ? PIC_FN_ADDR_REG :
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@ -8541,20 +8550,6 @@ mips_secondary_reload_class (class, mode, x, in_p)
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&& DANGEROUS_FOR_LA25_P (x))
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return LEA_REGS;
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/* We always require a general register when copying anything to
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HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
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to a general register, or when copying from register 0. */
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if (class == HILO_REG && regno != GP_REG_FIRST + 0)
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return ((! in_p
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&& gp_reg_p
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&& GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
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? NO_REGS : gr_regs);
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else if (regno == HILO_REGNUM)
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return ((in_p
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&& class == gr_regs
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&& GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
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? NO_REGS : gr_regs);
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/* Copying from HI or LO to anywhere other than a general register
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requires a general register. */
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if (class == HI_REG || class == LO_REG || class == MD_REGS)
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@ -8636,19 +8631,6 @@ mips_secondary_reload_class (class, mode, x, in_p)
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}
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if (! gp_reg_p)
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{
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/* The stack pointer isn't a valid operand to an add instruction,
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so we need to load it into M16_REGS first. This can happen as
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a result of register elimination and form_sum converting
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(plus reg (plus SP CONST)) to (plus (plus reg SP) CONST). We
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need an extra register if the dest is the same as the other
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register. In that case, we can't fix the problem by loading SP
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into the dest first. */
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if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == REG
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&& GET_CODE (XEXP (x, 1)) == REG
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&& (XEXP (x, 0) == stack_pointer_rtx
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|| XEXP (x, 1) == stack_pointer_rtx))
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return (class == M16_REGS ? M16_NA_REGS : M16_REGS);
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if (class == M16_REGS || class == M16_NA_REGS)
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return NO_REGS;
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return M16_REGS;
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@ -9775,10 +9757,10 @@ mips_reorg ()
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should do this if the `movM' pattern's constraints do not allow
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such copying.
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??? We make make the cost of moving from HI/LO/HILO/MD into general
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??? We make the cost of moving from HI/LO into general
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registers the same as for one of moving general registers to
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HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
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pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
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HI/LO for TARGET_MIPS16 in order to prevent allocating a
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pseudo to HI/LO. This might hurt optimizations though, it
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isn't clear if it is wise. And it might not work in all cases. We
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could solve the DImode LO reg problem by using a multiply, just
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like reload_{in,out}si. We could solve the SImode/HImode HI reg
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@ -9813,8 +9795,7 @@ mips_register_move_cost (mode, to, from)
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}
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else if (to == FP_REGS)
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return 4;
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else if (to == HI_REG || to == LO_REG || to == MD_REGS
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|| to == HILO_REG)
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else if (to == HI_REG || to == LO_REG || to == MD_REGS)
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{
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if (TARGET_MIPS16)
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return 12;
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@ -9835,8 +9816,7 @@ mips_register_move_cost (mode, to, from)
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else if (to == ST_REGS)
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return 8;
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} /* from == FP_REGS */
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else if (from == HI_REG || from == LO_REG || from == MD_REGS
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|| from == HILO_REG)
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else if (from == HI_REG || from == LO_REG || from == MD_REGS)
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{
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if (GR_REG_CLASS_P (to))
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{
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@ -1683,14 +1683,9 @@ do { \
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On the Mips, we have 32 integer registers, 32 floating point
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registers, 8 condition code registers, and the special registers
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hi, lo, hilo, and rap. Afetr that we have 32 COP0 registers, 32
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COP2 registers, and 32 COp3 registers. (COP1 is the floating-point
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processor.) The 8 condition code registers are only used if
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mips_isa >= 4. The hilo register is only used in 64 bit mode. It
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represents a 64 bit value stored as two 32 bit values in the hi and
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lo registers; this is the result of the mult instruction. rap is a
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pointer to the stack where the return address reg ($31) was stored.
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This is needed for C++ exception handling. */
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hi and lo. After that we have 32 COP0 registers, 32 COP2 registers,
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and 32 COP3 registers. (COP1 is the floating-point processor.)
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The 8 condition code registers are only used if mips_isa >= 4. */
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#define FIRST_PSEUDO_REGISTER 176
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@ -1711,7 +1706,7 @@ do { \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
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0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
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/* COP0 registers */ \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
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@ -1795,7 +1790,7 @@ do { \
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#define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
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#define MD_REG_FIRST 64
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#define MD_REG_LAST 66
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#define MD_REG_LAST 65
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#define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
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#define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
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@ -1822,7 +1817,6 @@ do { \
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#define AT_REGNUM (GP_REG_FIRST + 1)
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#define HI_REGNUM (MD_REG_FIRST + 0)
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#define LO_REGNUM (MD_REG_FIRST + 1)
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#define HILO_REGNUM (MD_REG_FIRST + 2)
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/* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
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mips_isa >= 4, it should not be used, and an arbitrary ST_REG
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@ -2002,14 +1996,12 @@ enum reg_class
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FP_REGS, /* floating point registers */
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HI_REG, /* hi register */
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LO_REG, /* lo register */
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HILO_REG, /* hilo register pair for 64 bit mode mult */
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MD_REGS, /* multiply/divide registers (hi/lo) */
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COP0_REGS, /* generic coprocessor classes */
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COP2_REGS,
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COP3_REGS,
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HI_AND_GR_REGS, /* union classes */
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LO_AND_GR_REGS,
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HILO_AND_GR_REGS,
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HI_AND_FP_REGS,
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COP0_AND_GR_REGS,
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COP2_AND_GR_REGS,
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@ -2042,7 +2034,6 @@ enum reg_class
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"FP_REGS", \
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"HI_REG", \
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"LO_REG", \
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"HILO_REG", \
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"MD_REGS", \
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/* coprocessor registers */ \
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"COP0_REGS", \
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@ -2050,7 +2041,6 @@ enum reg_class
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"COP3_REGS", \
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"HI_AND_GR_REGS", \
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"LO_AND_GR_REGS", \
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"HILO_AND_GR_REGS", \
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"HI_AND_FP_REGS", \
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"COP0_AND_GR_REGS", \
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"COP2_AND_GR_REGS", \
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@ -2085,14 +2075,12 @@ enum reg_class
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{ 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
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{ 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
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{ 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
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{ 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* hilo register */ \
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{ 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
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{ 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
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{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
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{ 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
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{ 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
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{ 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \
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{ 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
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{ 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
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{ 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
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@ -2186,7 +2174,6 @@ extern const enum reg_class mips_regno_to_class[];
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'h' Hi register
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'l' Lo register
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'x' Multiply/divide registers
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'a' HILO_REG
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'z' FP Status register
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'B' Cop0 register
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'C' Cop2 register
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@ -3312,7 +3299,8 @@ typedef struct mips_args {
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{"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
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CONST_DOUBLE, CONST }}, \
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{"fcc_register_operand", { REG, SUBREG }}, \
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{"hilo_operand", { REG }},
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{"hilo_operand", { REG }}, \
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{"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
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/* A list of predicates that do special things with modes, and so
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should not elicit warnings for VOIDmode match_operand. */
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@ -3546,7 +3534,7 @@ typedef struct mips_args {
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"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
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"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
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"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
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"hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
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"hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
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"$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
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"$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
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"$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
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