aarch64: Improve cas generation
Do not zero-extend the input to the cas for subword operations; instead, use the appropriate zero-extending compare insns. Correct the predicates and constraints for immediate expected operand. * config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): New. (aarch64_split_compare_and_swap): Use it. (aarch64_expand_compare_and_swap): Likewise. Remove convert_modes; test oldval against the proper predicate. * config/aarch64/atomics.md (@atomic_compare_and_swap<ALLI>): Use nonmemory_operand for expected. (cas_short_expected_pred): New. (@aarch64_compare_and_swap<SHORT>): Use it; use "rn" not "rI" to match. (@aarch64_compare_and_swap<GPI>): Use "rn" not "rI" for expected. * config/aarch64/predicates.md (aarch64_plushi_immediate): New. (aarch64_plushi_operand): New. From-SVN: r265657
This commit is contained in:
Richard Henderson
Richard Henderson
parent
77f33f44ba
commit
d400fda3a8
@ -1,5 +1,17 @@
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2018-10-31 Richard Henderson <richard.henderson@linaro.org>
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* config/aarch64/aarch64.c (aarch64_gen_compare_reg_maybe_ze): New.
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(aarch64_split_compare_and_swap): Use it.
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(aarch64_expand_compare_and_swap): Likewise. Remove convert_modes;
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test oldval against the proper predicate.
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* config/aarch64/atomics.md (@atomic_compare_and_swap<ALLI>):
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Use nonmemory_operand for expected.
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(cas_short_expected_pred): New.
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(@aarch64_compare_and_swap<SHORT>): Use it; use "rn" not "rI" to match.
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(@aarch64_compare_and_swap<GPI>): Use "rn" not "rI" for expected.
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* config/aarch64/predicates.md (aarch64_plushi_immediate): New.
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(aarch64_plushi_operand): New.
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* config/aarch64/aarch64.c (aarch64_expand_compare_and_swap):
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Force oldval into the rval register for TARGET_LSE; emit the compare
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during initial expansion so that it may be deleted if unused.
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@ -1614,6 +1614,33 @@ aarch64_gen_compare_reg (RTX_CODE code, rtx x, rtx y)
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return cc_reg;
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}
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/* Similarly, but maybe zero-extend Y if Y_MODE < SImode. */
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static rtx
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aarch64_gen_compare_reg_maybe_ze (RTX_CODE code, rtx x, rtx y,
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machine_mode y_mode)
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{
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if (y_mode == E_QImode || y_mode == E_HImode)
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{
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if (CONST_INT_P (y))
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y = GEN_INT (INTVAL (y) & GET_MODE_MASK (y_mode));
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else
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{
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rtx t, cc_reg;
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machine_mode cc_mode;
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t = gen_rtx_ZERO_EXTEND (SImode, y);
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t = gen_rtx_COMPARE (CC_SWPmode, t, x);
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cc_mode = CC_SWPmode;
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cc_reg = gen_rtx_REG (cc_mode, CC_REGNUM);
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emit_set_insn (cc_reg, t);
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return cc_reg;
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}
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}
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return aarch64_gen_compare_reg (code, x, y);
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}
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/* Build the SYMBOL_REF for __tls_get_addr. */
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static GTY(()) rtx tls_get_addr_libfunc;
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@ -14575,8 +14602,8 @@ aarch64_emit_unlikely_jump (rtx insn)
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void
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aarch64_expand_compare_and_swap (rtx operands[])
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{
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rtx bval, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x;
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machine_mode mode, cmp_mode;
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rtx bval, rval, mem, oldval, newval, is_weak, mod_s, mod_f, x, cc_reg;
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machine_mode mode, r_mode;
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bval = operands[0];
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rval = operands[1];
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@ -14587,36 +14614,19 @@ aarch64_expand_compare_and_swap (rtx operands[])
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mod_s = operands[6];
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mod_f = operands[7];
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mode = GET_MODE (mem);
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cmp_mode = mode;
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/* Normally the succ memory model must be stronger than fail, but in the
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unlikely event of fail being ACQUIRE and succ being RELEASE we need to
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promote succ to ACQ_REL so that we don't lose the acquire semantics. */
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if (is_mm_acquire (memmodel_from_int (INTVAL (mod_f)))
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&& is_mm_release (memmodel_from_int (INTVAL (mod_s))))
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mod_s = GEN_INT (MEMMODEL_ACQ_REL);
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switch (mode)
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r_mode = mode;
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if (mode == QImode || mode == HImode)
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{
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case E_QImode:
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case E_HImode:
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/* For short modes, we're going to perform the comparison in SImode,
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so do the zero-extension now. */
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cmp_mode = SImode;
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rval = gen_reg_rtx (SImode);
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oldval = convert_modes (SImode, mode, oldval, true);
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/* Fall through. */
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case E_SImode:
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case E_DImode:
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/* Force the value into a register if needed. */
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if (!aarch64_plus_operand (oldval, mode))
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oldval = force_reg (cmp_mode, oldval);
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break;
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default:
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gcc_unreachable ();
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r_mode = SImode;
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rval = gen_reg_rtx (r_mode);
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}
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if (TARGET_LSE)
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@ -14624,26 +14634,32 @@ aarch64_expand_compare_and_swap (rtx operands[])
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/* The CAS insn requires oldval and rval overlap, but we need to
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have a copy of oldval saved across the operation to tell if
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the operation is successful. */
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if (mode == QImode || mode == HImode)
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rval = copy_to_mode_reg (SImode, gen_lowpart (SImode, oldval));
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else if (reg_overlap_mentioned_p (rval, oldval))
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rval = copy_to_mode_reg (mode, oldval);
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if (reg_overlap_mentioned_p (rval, oldval))
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rval = copy_to_mode_reg (r_mode, oldval);
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else
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emit_move_insn (rval, oldval);
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emit_move_insn (rval, gen_lowpart (r_mode, oldval));
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emit_insn (gen_aarch64_compare_and_swap_lse (mode, rval, mem,
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newval, mod_s));
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aarch64_gen_compare_reg (EQ, rval, oldval);
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cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
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}
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else
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emit_insn (gen_aarch64_compare_and_swap (mode, rval, mem, oldval, newval,
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is_weak, mod_s, mod_f));
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{
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/* The oldval predicate varies by mode. Test it and force to reg. */
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insn_code code = code_for_aarch64_compare_and_swap (mode);
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if (!insn_data[code].operand[2].predicate (oldval, mode))
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oldval = force_reg (mode, oldval);
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if (mode == QImode || mode == HImode)
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emit_insn (GEN_FCN (code) (rval, mem, oldval, newval,
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is_weak, mod_s, mod_f));
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cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
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}
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if (r_mode != mode)
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rval = gen_lowpart (mode, rval);
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emit_move_insn (operands[1], rval);
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x = gen_rtx_REG (CCmode, CC_REGNUM);
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x = gen_rtx_EQ (SImode, x, const0_rtx);
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x = gen_rtx_EQ (SImode, cc_reg, const0_rtx);
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emit_insn (gen_rtx_SET (bval, x));
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}
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@ -14758,10 +14774,10 @@ aarch64_split_compare_and_swap (rtx operands[])
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}
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else
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{
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cond = aarch64_gen_compare_reg (NE, rval, oldval);
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cond = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
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x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
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x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
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gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
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gen_rtx_LABEL_REF (Pmode, label2), pc_rtx);
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aarch64_emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
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}
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@ -24,8 +24,8 @@
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[(match_operand:SI 0 "register_operand" "") ;; bool out
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(match_operand:ALLI 1 "register_operand" "") ;; val out
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(match_operand:ALLI 2 "aarch64_sync_memory_operand" "") ;; memory
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(match_operand:ALLI 3 "general_operand" "") ;; expected
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(match_operand:ALLI 4 "aarch64_reg_or_zero" "") ;; desired
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(match_operand:ALLI 3 "nonmemory_operand" "") ;; expected
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(match_operand:ALLI 4 "aarch64_reg_or_zero" "") ;; desired
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(match_operand:SI 5 "const_int_operand") ;; is_weak
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(match_operand:SI 6 "const_int_operand") ;; mod_s
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(match_operand:SI 7 "const_int_operand")] ;; mod_f
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@ -36,19 +36,22 @@
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}
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)
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(define_mode_attr cas_short_expected_pred
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[(QI "aarch64_reg_or_imm") (HI "aarch64_plushi_operand")])
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(define_insn_and_split "@aarch64_compare_and_swap<mode>"
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[(set (reg:CC CC_REGNUM) ;; bool out
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(unspec_volatile:CC [(const_int 0)] UNSPECV_ATOMIC_CMPSW))
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(set (match_operand:SI 0 "register_operand" "=&r") ;; val out
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(set (match_operand:SI 0 "register_operand" "=&r") ;; val out
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(zero_extend:SI
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(match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
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(set (match_dup 1)
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(unspec_volatile:SHORT
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[(match_operand:SI 2 "aarch64_plus_operand" "rI") ;; expected
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[(match_operand:SHORT 2 "<cas_short_expected_pred>" "rn") ;; expected
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(match_operand:SHORT 3 "aarch64_reg_or_zero" "rZ") ;; desired
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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(match_operand:SI 6 "const_int_operand")] ;; mod_f
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UNSPECV_ATOMIC_CMPSW))
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(clobber (match_scratch:SI 7 "=&r"))]
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""
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@ -68,7 +71,7 @@
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(match_operand:GPI 1 "aarch64_sync_memory_operand" "+Q")) ;; memory
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(set (match_dup 1)
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(unspec_volatile:GPI
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[(match_operand:GPI 2 "aarch64_plus_operand" "rI") ;; expect
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[(match_operand:GPI 2 "aarch64_plus_operand" "rn") ;; expect
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(match_operand:GPI 3 "aarch64_reg_or_zero" "rZ") ;; desired
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(match_operand:SI 4 "const_int_operand") ;; is_weak
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(match_operand:SI 5 "const_int_operand") ;; mod_s
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@ -114,6 +114,18 @@
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "aarch64_plus_immediate")))
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(define_predicate "aarch64_plushi_immediate"
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(match_code "const_int")
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{
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HOST_WIDE_INT val = INTVAL (op);
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/* The HImode value must be zero-extendable to an SImode plus_operand. */
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return ((val & 0xfff) == val || sext_hwi (val & 0xf000, 16) == val);
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})
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(define_predicate "aarch64_plushi_operand"
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(ior (match_operand 0 "register_operand")
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(match_operand 0 "aarch64_plushi_immediate")))
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(define_predicate "aarch64_pluslong_immediate"
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(and (match_code "const_int")
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(match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
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