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[ARC] Rework ARC600 64-bit multiplication patterns.

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Previously users of mulsidi_600 and umulsidi_600 had to take care of
moving the multiplication result into the final destination themselves
(from the MUL64_OUT_REG register).  This commit converts these two
instruction patterns into insn_and_split patterns that now take the
final destination as an extra operand.  The insn_and_split patterns
generate the multiplication using two new multiplication instruction
patterns, then generate the move of the result from the MUL64_OUT_REG
register into the final destination.

This is a clean up commit, there should be no user visible changes
after this commit.

2016-12-16  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (mulsidi_600): Change to insn_and_split,
	generate new mul64 insn for core multiplication work.
	(umulsidi_600): Likewise, but use mulu64 insn.
	(mul64): New pattern, content taken from old mulsidi_600 insn
	pattern.
	(mulu64): Likewise, but using umulsidi_600.
	(mulsidi3): Remove move to destination, this is now handled by
	mulsidi_600 insn_and_split.
	(umulsidi3): Likewise, but using umulsidi_600.

From-SVN: r243741
This commit is contained in:
Claudiu Zissulescu 2016-12-16 13:56:09 +01:00 committed by Claudiu Zissulescu
parent cc0ca4999b
commit d476b53c36
2 changed files with 52 additions and 24 deletions
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12
gcc/ChangeLog
View File

@ -1,3 +1,15 @@
2016-12-16 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (mulsidi_600): Change to insn_and_split,
generate new mul64 insn for core multiplication work.
(umulsidi_600): Likewise, but use mulu64 insn.
(mul64): New pattern, content taken from old mulsidi_600 insn
pattern.
(mulu64): Likewise, but using umulsidi_600.
(mulsidi3): Remove move to destination, this is now handled by
mulsidi_600 insn_and_split.
(umulsidi3): Likewise, but using umulsidi_600.
2016-12-16 Richard Biener <rguenther@suse.de>
PR c++/71694

64
gcc/config/arc/arc.md
View File

@ -12,10 +12,6 @@
;; Profiling support and performance improvements by
;; Joern Rennecke (joern.rennecke@embecosm.com)
;;
;; Support for DSP multiply instructions and mul64
;; instructions for ARC600; and improvements in flag setting
;; instructions by
;; Muhammad Khurram Riaz (Khurram.Riaz@arc.com)
;; This file is part of GCC.
@ -2054,14 +2050,26 @@
[(set_attr "is_sfunc" "yes")
(set_attr "predicable" "yes")])
(define_insn "mulsidi_600"
(define_insn_and_split "mulsidi_600"
[(set (match_operand:DI 0 "register_operand" "=c, c,c, c")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%Rcq#q, c,c, c"))
(sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "Rcq#q,cL,L,C32"))))
(clobber (reg:DI MUL64_OUT_REG))]
"TARGET_MUL64_SET"
"#"
"TARGET_MUL64_SET"
[(const_int 0)]
"emit_insn (gen_mul64 (operands[1], operands[2]));
emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG));
DONE;"
[(set_attr "type" "multi")
(set_attr "length" "8")])
(define_insn "mul64"
[(set (reg:DI MUL64_OUT_REG)
(mult:DI (sign_extend:DI
(match_operand:SI 0 "register_operand" "%Rcq#q,c,c,c"))
(sign_extend:DI
; assembler issue for "I", see mulsi_600
; (match_operand:SI 1 "register_operand" "Rcq#q,cL,I,Cal"))))]
(match_operand:SI 1 "register_operand" "Rcq#q,cL,L,C32"))))]
(mult:DI
(sign_extend:DI (match_operand:SI 0 "register_operand" "%Rcq#q, c,c, c"))
(sign_extend:DI (match_operand:SI 1 "nonmemory_operand" "Rcq#q,cL,L,C32"))))]
"TARGET_MUL64_SET"
"mul64%? \t0, %0, %1%&"
[(set_attr "length" "*,4,4,8")
@ -2070,14 +2078,26 @@
(set_attr "predicable" "yes,yes,no,yes")
(set_attr "cond" "canuse,canuse,canuse_limm,canuse")])
(define_insn "umulsidi_600"
(define_insn_and_split "umulsidi_600"
[(set (match_operand:DI 0 "register_operand" "=c,c, c")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%c,c, c"))
(sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "cL,L,C32"))))
(clobber (reg:DI MUL64_OUT_REG))]
"TARGET_MUL64_SET"
"#"
"TARGET_MUL64_SET"
[(const_int 0)]
"emit_insn (gen_mulu64 (operands[1], operands[2]));
emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG));
DONE;"
[(set_attr "type" "umulti")
(set_attr "length" "8")])
(define_insn "mulu64"
[(set (reg:DI MUL64_OUT_REG)
(mult:DI (zero_extend:DI
(match_operand:SI 0 "register_operand" "%c,c,c"))
(sign_extend:DI
; assembler issue for "I", see mulsi_600
; (match_operand:SI 1 "register_operand" "cL,I,Cal"))))]
(match_operand:SI 1 "register_operand" "cL,L,C32"))))]
(mult:DI
(zero_extend:DI (match_operand:SI 0 "register_operand" "%c,c,c"))
(zero_extend:DI (match_operand:SI 1 "nonmemory_operand" "cL,L,C32"))))]
"TARGET_MUL64_SET"
"mulu64%? \t0, %0, %1%&"
[(set_attr "length" "4,4,8")
@ -2141,9 +2161,7 @@
}
else if (TARGET_MUL64_SET)
{
operands[2] = force_reg (SImode, operands[2]);
emit_insn (gen_mulsidi_600 (operands[1], operands[2]));
emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG));
emit_insn (gen_mulsidi_600 (operands[0], operands[1], operands[2]));
DONE;
}
else if (TARGET_MULMAC_32BY16_SET)
@ -2375,9 +2393,7 @@
}
else if (TARGET_MUL64_SET)
{
operands[2] = force_reg (SImode, operands[2]);
emit_insn (gen_umulsidi_600 (operands[1], operands[2]));
emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG));
emit_insn (gen_umulsidi_600 (operands[0], operands[1], operands[2]));
DONE;
}
else if (TARGET_MULMAC_32BY16_SET)