aarch64: Don't emit invalid zero/sign-extend syntax
Given the following C function:
double *f(double *p, unsigned x)
{
return p + x;
}
prior to this patch, GCC at -O2 would generate:
f:
add x0, x0, x1, uxtw 3
ret
but this add instruction uses architecturally-invalid syntax: the width
of the third operand conflicts with the width of the extension
specifier. The third operand is only permitted to be an x register when
the extension specifier is (u|s)xtx.
This instruction, and analogous insns for adds, sub, subs, and cmp, are
rejected by clang, but accepted by binutils. Assembling and
disassembling such an insn with binutils gives the architecturally-valid
version in the disassembly:
0: 8b214c00 add x0, x0, w1, uxtw #3
This patch fixes several patterns in the AArch64 backend to use the
standard syntax as specified in the Arm ARM such that GCC's output can
be assembled by assemblers other than GAS.
---
gcc/ChangeLog:
* config/aarch64/aarch64.md
(*adds_<optab><ALLX:mode>_<GPI:mode>): Ensure extended operand
agrees with width of extension specifier.
(*subs_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*adds_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise.
(*subs_<optab><ALLX:mode>_shift_<GPI:mode>): Likewise.
(*add_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*add_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise.
(*add_uxt<mode>_shift2): Likewise.
(*sub_<optab><ALLX:mode>_<GPI:mode>): Likewise.
(*sub_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise.
(*sub_uxt<mode>_shift2): Likewise.
(*cmp_swp_<optab><ALLX:mode>_reg<GPI:mode>): Likewise.
(*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/adds3.c: Fix test w.r.t. new syntax.
* gcc.target/aarch64/cmp.c: Likewise.
* gcc.target/aarch64/subs3.c: Likewise.
* gcc.target/aarch64/subsp.c: Likewise.
* gcc.target/aarch64/extend-syntax.c: New test.
This commit is contained in:
Alex Coplan
parent
931832a5cc
commit
d4febc75e8
@ -2383,7 +2383,7 @@
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(set (match_operand:GPI 0 "register_operand" "=r")
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(plus:GPI (ANY_EXTEND:GPI (match_dup 1)) (match_dup 2)))]
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""
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"adds\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>"
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"adds\\t%<GPI:w>0, %<GPI:w>2, %w1, <su>xt<ALLX:size>"
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[(set_attr "type" "alus_ext")]
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)
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@ -2397,7 +2397,7 @@
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(set (match_operand:GPI 0 "register_operand" "=r")
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(minus:GPI (match_dup 1) (ANY_EXTEND:GPI (match_dup 2))))]
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""
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"subs\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>"
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"subs\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size>"
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[(set_attr "type" "alus_ext")]
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)
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@ -2415,7 +2415,7 @@
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(match_dup 2))
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(match_dup 3)))]
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""
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"adds\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %2"
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"adds\\t%<GPI:w>0, %<GPI:w>3, %w1, <su>xt<ALLX:size> %2"
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[(set_attr "type" "alus_ext")]
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)
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@ -2433,7 +2433,7 @@
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(ashift:GPI (ANY_EXTEND:GPI (match_dup 2))
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(match_dup 3))))]
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""
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"subs\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size> %3"
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"subs\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size> %3"
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[(set_attr "type" "alus_ext")]
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)
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@ -2549,7 +2549,7 @@
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(plus:GPI (ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r"))
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(match_operand:GPI 2 "register_operand" "r")))]
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""
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"add\\t%<GPI:w>0, %<GPI:w>2, %<GPI:w>1, <su>xt<ALLX:size>"
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"add\\t%<GPI:w>0, %<GPI:w>2, %w1, <su>xt<ALLX:size>"
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[(set_attr "type" "alu_ext")]
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)
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@ -2571,7 +2571,7 @@
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(match_operand 2 "aarch64_imm3" "Ui3"))
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(match_operand:GPI 3 "register_operand" "r")))]
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""
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"add\\t%<GPI:w>0, %<GPI:w>3, %<GPI:w>1, <su>xt<ALLX:size> %2"
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"add\\t%<GPI:w>0, %<GPI:w>3, %w1, <su>xt<ALLX:size> %2"
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[(set_attr "type" "alu_ext")]
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)
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@ -2819,7 +2819,7 @@
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"*
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operands[3] = GEN_INT (aarch64_uxt_size (INTVAL(operands[2]),
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INTVAL (operands[3])));
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return \"add\t%<w>0, %<w>4, %<w>1, uxt%e3 %2\";"
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return \"add\t%<w>0, %<w>4, %w1, uxt%e3 %2\";"
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[(set_attr "type" "alu_ext")]
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)
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@ -3305,7 +3305,7 @@
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(ANY_EXTEND:GPI
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(match_operand:ALLX 2 "register_operand" "r"))))]
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""
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"sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size>"
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"sub\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size>"
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[(set_attr "type" "alu_ext")]
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)
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@ -3328,7 +3328,7 @@
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(match_operand:ALLX 2 "register_operand" "r"))
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(match_operand 3 "aarch64_imm3" "Ui3"))))]
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""
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"sub\\t%<GPI:w>0, %<GPI:w>1, %<GPI:w>2, <su>xt<ALLX:size> %3"
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"sub\\t%<GPI:w>0, %<GPI:w>1, %w2, <su>xt<ALLX:size> %3"
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[(set_attr "type" "alu_ext")]
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)
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@ -3607,7 +3607,7 @@
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"*
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operands[3] = GEN_INT (aarch64_uxt_size (INTVAL (operands[2]),
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INTVAL (operands[3])));
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return \"sub\t%<w>0, %<w>4, %<w>1, uxt%e3 %2\";"
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return \"sub\t%<w>0, %<w>4, %w1, uxt%e3 %2\";"
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[(set_attr "type" "alu_ext")]
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)
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@ -4054,7 +4054,7 @@
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(match_operand:ALLX 0 "register_operand" "r"))
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(match_operand:GPI 1 "register_operand" "r")))]
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""
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"cmp\\t%<GPI:w>1, %<GPI:w>0, <su>xt<ALLX:size>"
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"cmp\\t%<GPI:w>1, %w0, <su>xt<ALLX:size>"
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[(set_attr "type" "alus_ext")]
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)
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@ -4066,7 +4066,7 @@
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(match_operand 1 "aarch64_imm3" "Ui3"))
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(match_operand:GPI 2 "register_operand" "r")))]
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""
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"cmp\\t%<GPI:w>2, %<GPI:w>0, <su>xt<ALLX:size> %1"
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"cmp\\t%<GPI:w>2, %w0, <su>xt<ALLX:size> %1"
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[(set_attr "type" "alus_ext")]
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)
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@ -58,4 +58,4 @@ int main ()
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return 0;
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}
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/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */
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/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw" 2 } } */
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@ -58,4 +58,5 @@ cmp_di_test4 (int a, s64 b, s64 c)
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}
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/* { dg-final { scan-assembler-times "cmp\tw\[0-9\]+, w\[0-9\]+" 2 } } */
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/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 4 } } */
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/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, x\[0-9\]+" 2 } } */
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/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, w\[0-9\]+, sxtw" 2 } } */
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120
gcc/testsuite/gcc.target/aarch64/extend-syntax.c
Normal file
120
gcc/testsuite/gcc.target/aarch64/extend-syntax.c
Normal file
@ -0,0 +1,120 @@
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/* { dg-do compile } */
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/* { dg-options "-O2" } */
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// Hits *add_uxtdi_shift2 (*add_uxt<mode>_shift2).
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/*
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** add1:
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** add x0, x0, w1, uxtw 3
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** ret
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*/
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unsigned long long *add1(unsigned long long *p, unsigned x)
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{
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return p + x;
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}
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// Hits *add_zero_extendsi_di (*add_<optab><ALLX:mode>_<GPI:mode>).
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/*
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** add2:
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** add x0, x0, w1, uxtw
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** ret
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*/
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unsigned long long add2(unsigned long long x, unsigned y)
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{
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return x + y;
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}
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// Hits *add_extendsi_shft_di (*add_<optab><ALLX:mode>_shft_<GPI:mode>).
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/*
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** add3:
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** add x0, x0, w1, sxtw 3
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** ret
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*/
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double *add3(double *p, int x)
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{
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return p + x;
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}
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// Hits *sub_zero_extendsi_di (*sub_<optab><ALLX:mode>_<GPI:mode>).
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/*
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** sub1:
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** sub x0, x0, w1, uxtw
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** ret
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*/
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unsigned long long sub1(unsigned long long x, unsigned n)
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{
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return x - n;
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}
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// Hits *sub_uxtdi_shift2 (*sub_uxt<mode>_shift2).
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/*
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** sub2:
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** sub x0, x0, w1, uxtw 3
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** ret
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*/
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double *sub2(double *x, unsigned n)
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{
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return x - n;
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}
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// Hits *sub_extendsi_shft_di (*sub_<optab><ALLX:mode>_shft_<GPI:mode>).
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/*
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** sub3:
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** sub x0, x0, w1, sxtw 3
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** ret
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*/
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double *sub3(double *p, int n)
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{
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return p - n;
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}
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// Hits *adds_zero_extendsi_di (*adds_<optab><ALLX:mode>_<GPI:mode>).
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int adds1(unsigned long long x, unsigned y)
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{
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/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, uxtw" 1 } } */
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unsigned long long l = x + y;
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return !!l;
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}
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// Hits *adds_extendsi_shift_di (*adds_<optab><ALLX:mode>_shift_<GPI:mode>).
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int adds2(long long x, int y)
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{
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/* { dg-final { scan-assembler-times "adds\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw 3" 1 } } */
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long long t = x + ((long long)y << 3);
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return !!t;
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}
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// Hits *subs_zero_extendsi_di (*subs_<optab><ALLX:mode>_<GPI:mode>).
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unsigned long long z;
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int subs1(unsigned long long x, unsigned y)
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{
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/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, uxtw" 1 } } */
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unsigned long long t = x - y;
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z = t;
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return !!t;
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}
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// Hits *subs_extendsi_shift_di (*subs_<optab><ALLX:mode>_shift_<GPI:mode>).
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unsigned long long *w;
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int subs2(unsigned long long *x, int y)
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{
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/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw 3" 1 } } */
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unsigned long long *t = x - y;
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w = t;
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return !!t;
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}
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// Hits *cmp_swp_zero_extendsi_regdi (*cmp_swp_<optab><ALLX:mode>_reg<GPI:mode>).
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int cmp(unsigned long long x, unsigned y)
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{
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/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, w\[0-9\]+, uxtw" 1 } } */
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return !!(x - y);
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}
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// Hits *cmp_swp_extendsi_shft_di (*cmp_swp_<optab><ALLX:mode>_shft_<GPI:mode>).
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int cmp2(unsigned long long x, int y)
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{
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/* { dg-final { scan-assembler-times "cmp\tx\[0-9\]+, w\[0-9\]+, sxtw 3" 1 } } */
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return x == ((unsigned long long)y << 3);
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}
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/* { dg-final { check-function-bodies "**" "" "" } } */
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@ -58,4 +58,4 @@ int main ()
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return 0;
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}
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/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, sxtw" 2 } } */
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/* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw" 2 } } */
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@ -16,4 +16,4 @@ f2 (int *x, int y)
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}
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/* { dg-final { scan-assembler "sub\tsp, sp, x\[0-9\]*\n" } } */
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/* { dg-final { scan-assembler "sub\tsp, sp, x\[0-9\]*, sxtw 4\n" } } */
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/* { dg-final { scan-assembler "sub\tsp, sp, w\[0-9\]*, sxtw 4\n" } } */
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