toplev.c (display_target_options): Avoid unused variable warning if TARGET_SWITCHES and TARGET_OPTIONS are both...
* toplev.c (display_target_options): Avoid unused variable warning if TARGET_SWITCHES and TARGET_OPTIONS are both undefined. * config/mips/mips.c (mips_arch_string, mips_tune_string): Make static. (mips_isa_string, mips_abi_string, mips_fix_vr4130_string): Delete. (mips_isa): Initialize to MIPS_ABI_DEFAULT. (mips_isa_info): New variable. (mips_parse_cpu): Remove the first argument and leave the caller to report errors. (TARGET_HANDLE_OPTION): Override default. (mips_handle_option): New function. Move option validation code from... (override_options): ...here. Update calls to mips_parse_cpu. * config/mips/mips.h (mips_arch_string, mips_tune_string) (mips_isa_string, mips_abi_string, TARGET_OPTIONS) (SUBTARGET_TARGET_OPTIONS): Delete. * config/mips/mips.opt (mabi=, march=, mflush-func=, mips) (mno-flush-func, mtune=): New options. From-SVN: r96536
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
cf1665b99c
commit
d522e7a222
@ -1,3 +1,22 @@
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2005-03-15 Richard Sandiford <rsandifo@redhat.com>
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* toplev.c (display_target_options): Avoid unused variable warning if
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TARGET_SWITCHES and TARGET_OPTIONS are both undefined.
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* config/mips/mips.c (mips_arch_string, mips_tune_string): Make static.
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(mips_isa_string, mips_abi_string, mips_fix_vr4130_string): Delete.
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(mips_isa): Initialize to MIPS_ABI_DEFAULT.
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(mips_isa_info): New variable.
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(mips_parse_cpu): Remove the first argument and leave the caller
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to report errors.
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(TARGET_HANDLE_OPTION): Override default.
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(mips_handle_option): New function. Move option validation code from...
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(override_options): ...here. Update calls to mips_parse_cpu.
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* config/mips/mips.h (mips_arch_string, mips_tune_string)
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(mips_isa_string, mips_abi_string, TARGET_OPTIONS)
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(SUBTARGET_TARGET_OPTIONS): Delete.
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* config/mips/mips.opt (mabi=, march=, mflush-func=, mips)
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(mno-flush-func, mtune=): New options.
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2005-03-15 Roger Sayle <roger@eyesopen.com>
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Richard Henderson <rth@redhat.com>
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@ -264,6 +264,7 @@ static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
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static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
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static void mips_set_architecture (const struct mips_cpu_info *);
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static void mips_set_tune (const struct mips_cpu_info *);
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static bool mips_handle_option (size_t, const char *, int);
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static struct machine_function *mips_init_machine_status (void);
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static void print_operand_reloc (FILE *, rtx, const char **);
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#if TARGET_IRIX
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@ -328,7 +329,7 @@ static void mips_avoid_hazards (void);
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static void mips_reorg (void);
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static bool mips_strict_matching_cpu_name_p (const char *, const char *);
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static bool mips_matching_cpu_name_p (const char *, const char *);
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static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
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static const struct mips_cpu_info *mips_parse_cpu (const char *);
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static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
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static bool mips_return_in_memory (tree, tree);
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static bool mips_strict_argument_naming (CUMULATIVE_ARGS *);
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@ -547,13 +548,7 @@ const struct mips_cpu_info *mips_tune_info;
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int mips_isa;
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/* Which ABI to use. */
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int mips_abi;
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/* Strings to hold which cpu and instruction set architecture to use. */
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const char *mips_arch_string; /* for -march=<xxx> */
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const char *mips_tune_string; /* for -mtune=<xxx> */
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const char *mips_isa_string; /* for -mips{1,2,3,4} */
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const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
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int mips_abi = MIPS_ABI_DEFAULT;
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/* Whether we are generating mips16 hard float code. In mips16 mode
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we always set TARGET_SOFT_FLOAT; this variable is nonzero if
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@ -561,10 +556,14 @@ const char *mips_abi_string; /* for -mabi={32,n32,64,eabi} */
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should arrange to call mips32 hard floating point code. */
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int mips16_hard_float;
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const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
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/* The arguments passed to -march and -mtune. */
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static const char *mips_arch_string;
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static const char *mips_tune_string;
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/* Holds string <X> if -mfix-vr4130<X> was passed on the command line. */
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const char *mips_fix_vr4130_string;
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/* The architecture selected by -mipsN. */
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static const struct mips_cpu_info *mips_isa_info;
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const char *mips_cache_flush_func = CACHE_FLUSH_FUNC;
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/* If TRUE, we split addresses into their high and low parts in the RTL. */
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int mips_split_addresses;
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@ -754,6 +753,8 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
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| TARGET_FP_EXCEPTIONS_DEFAULT \
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| MASK_CHECK_ZERO_DIV \
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| MASK_FUSED_MADD)
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#undef TARGET_HANDLE_OPTION
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#define TARGET_HANDLE_OPTION mips_handle_option
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#undef TARGET_FUNCTION_OK_FOR_SIBCALL
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#define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
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@ -4191,6 +4192,52 @@ mips_set_tune (const struct mips_cpu_info *info)
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}
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}
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/* Implement TARGET_HANDLE_OPTION. */
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static bool
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mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
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{
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switch (code)
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{
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case OPT_mabi_:
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if (strcmp (arg, "32") == 0)
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mips_abi = ABI_32;
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else if (strcmp (arg, "o64") == 0)
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mips_abi = ABI_O64;
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else if (strcmp (arg, "n32") == 0)
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mips_abi = ABI_N32;
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else if (strcmp (arg, "64") == 0)
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mips_abi = ABI_64;
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else if (strcmp (arg, "eabi") == 0)
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mips_abi = ABI_EABI;
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else
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return false;
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return true;
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case OPT_march_:
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mips_arch_string = arg;
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return mips_parse_cpu (arg) != 0;
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case OPT_mtune_:
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mips_tune_string = arg;
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return mips_parse_cpu (arg) != 0;
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case OPT_mips:
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mips_isa_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
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return mips_isa_info != 0;
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case OPT_mflush_func_:
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mips_cache_flush_func = arg;
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return true;
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case OPT_mno_flush_func:
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mips_cache_flush_func = NULL;
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return true;
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default:
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return true;
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}
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}
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/* Set up the threshold for data to go into the small data area, instead
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of the normal data area, and detect any conflicts in the switches. */
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@ -4203,57 +4250,28 @@ override_options (void)
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mips_section_threshold = g_switch_set ? g_switch_value : MIPS_DEFAULT_GVALUE;
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/* Interpret -mabi. */
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mips_abi = MIPS_ABI_DEFAULT;
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if (mips_abi_string != 0)
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{
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if (strcmp (mips_abi_string, "32") == 0)
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mips_abi = ABI_32;
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else if (strcmp (mips_abi_string, "o64") == 0)
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mips_abi = ABI_O64;
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else if (strcmp (mips_abi_string, "n32") == 0)
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mips_abi = ABI_N32;
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else if (strcmp (mips_abi_string, "64") == 0)
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mips_abi = ABI_64;
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else if (strcmp (mips_abi_string, "eabi") == 0)
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mips_abi = ABI_EABI;
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else
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fatal_error ("bad value (%s) for -mabi= switch", mips_abi_string);
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}
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/* The following code determines the architecture and register size.
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Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
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The GAS and GCC code should be kept in sync as much as possible. */
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if (mips_arch_string != 0)
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mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
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mips_set_architecture (mips_parse_cpu (mips_arch_string));
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if (mips_isa_string != 0)
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if (mips_isa_info != 0)
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{
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/* Handle -mipsN. */
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char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
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const struct mips_cpu_info *isa_info;
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isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
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free (whole_isa_str);
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/* -march takes precedence over -mipsN, since it is more descriptive.
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There's no harm in specifying both as long as the ISA levels
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are the same. */
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if (mips_arch_info != 0 && mips_isa != isa_info->isa)
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error ("-mips%s conflicts with the other architecture options, "
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"which specify a MIPS%d processor",
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mips_isa_string, mips_isa);
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/* Set architecture based on the given option. */
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mips_set_architecture (isa_info);
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if (mips_arch_info == 0)
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mips_set_architecture (mips_isa_info);
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else if (mips_arch_info->isa != mips_isa_info->isa)
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error ("-%s conflicts with the other architecture options, "
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"which specify a %s processor",
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mips_isa_info->name,
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mips_cpu_info_from_isa (mips_arch_info->isa)->name);
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}
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if (mips_arch_info == 0)
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{
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#ifdef MIPS_CPU_STRING_DEFAULT
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mips_set_architecture (mips_parse_cpu ("default CPU",
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MIPS_CPU_STRING_DEFAULT));
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mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
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#else
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mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
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#endif
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@ -4265,7 +4283,7 @@ override_options (void)
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/* Optimize for mips_arch, unless -mtune selects a different processor. */
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if (mips_tune_string != 0)
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mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
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mips_set_tune (mips_parse_cpu (mips_tune_string));
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if (mips_tune_info == 0)
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mips_set_tune (mips_arch_info);
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@ -4336,9 +4354,6 @@ override_options (void)
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if (TARGET_INT64 && !TARGET_LONG64)
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error ("unsupported combination: %s", "-mint64 -mlong32");
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if (mips_fix_vr4130_string && mips_fix_vr4130_string[0] != 0)
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error ("unrecognized option %<-mfix-vr4130%s%>", mips_fix_vr4130_string);
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if (MIPS_MARCH_CONTROLS_SOFT_FLOAT
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&& (target_flags_explicit & MASK_SOFT_FLOAT) == 0)
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{
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@ -9177,15 +9192,13 @@ mips_matching_cpu_name_p (const char *canonical, const char *given)
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}
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/* Parse an option that takes the name of a processor as its argument.
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OPTION is the name of the option and CPU_STRING is the argument.
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Return the corresponding processor enumeration if the CPU_STRING is
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recognized, otherwise report an error and return null.
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/* Return the mips_cpu_info entry for the processor or ISA given
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by CPU_STRING. Return null if the string isn't recognised.
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A similar function exists in GAS. */
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static const struct mips_cpu_info *
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mips_parse_cpu (const char *option, const char *cpu_string)
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mips_parse_cpu (const char *cpu_string)
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{
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const struct mips_cpu_info *p;
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const char *s;
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@ -9217,7 +9230,6 @@ mips_parse_cpu (const char *option, const char *cpu_string)
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if (mips_matching_cpu_name_p (p->name, cpu_string))
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return p;
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error ("bad value (%s) for %s", cpu_string, option);
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return 0;
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}
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@ -102,10 +102,6 @@ extern enum processor_type mips_tune; /* which cpu to schedule for */
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extern int mips_isa; /* architectural level */
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extern int mips_abi; /* which ABI to use */
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extern int mips16_hard_float; /* mips16 without -msoft-float */
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extern const char *mips_arch_string; /* for -march=<xxx> */
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extern const char *mips_tune_string; /* for -mtune=<xxx> */
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extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
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extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
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extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
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extern const struct mips_cpu_info mips_cpu_info_table[];
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extern const struct mips_cpu_info *mips_arch_info;
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@ -486,26 +482,6 @@ extern const struct mips_cpu_info *mips_tune_info;
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#endif
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#endif
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#define TARGET_OPTIONS \
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{ \
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SUBTARGET_TARGET_OPTIONS \
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{ "tune=", &mips_tune_string, \
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N_("Specify CPU for scheduling purposes"), 0}, \
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{ "arch=", &mips_arch_string, \
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N_("Specify CPU for code generation purposes"), 0}, \
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{ "abi=", &mips_abi_string, \
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N_("Specify an ABI"), 0}, \
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{ "ips", &mips_isa_string, \
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N_("Specify a Standard MIPS ISA"), 0}, \
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{ "no-flush-func", &mips_cache_flush_func, \
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N_("Don't call any cache flush functions"), 0}, \
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{ "flush-func=", &mips_cache_flush_func, \
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N_("Specify cache flush function"), 0}, \
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}
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/* This is meant to be redefined in the host dependent files. */
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#define SUBTARGET_TARGET_OPTIONS
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/* Support for a compile-time default CPU, et cetera. The rules are:
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--with-arch is ignored if -march is specified or a -mips is specified
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(other than -mips16).
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@ -1,3 +1,7 @@
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mabi=
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Target RejectNegative Joined
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-mabi=ABI Generate code that conforms to the given ABI
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mabicalls
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Target Report Mask(ABICALLS)
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Use SVR4-style PIC
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@ -6,6 +10,10 @@ mad
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Target Report Var(TARGET_MAD)
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Use PMC-style 'mad' instructions
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march=
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Target RejectNegative Joined
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-march=ISA Generate code for the given ISA
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mbranch-likely
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Target Report Mask(BRANCHLIKELY)
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Use Branch Likely instructions, overriding the architecture default
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@ -84,6 +92,10 @@ mfp64
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Target Report RejectNegative Mask(FLOAT64)
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Use 64-bit floating-point registers
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mflush-func=
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Target RejectNegative Joined
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-mflush-func=FUNC Use FUNC to flush the cache before calling stack trampolines
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mfused-madd
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Target Report Mask(FUSED_MADD)
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Generate floating-point multiply-add instructions
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@ -104,6 +116,10 @@ mint64
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Target Report RejectNegative Mask(INT64)
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Use a 64-bit int type
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mips
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Target RejectNegative Joined
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-mipsN Generate code for ISA level N
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mips16
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Target Report RejectNegative Mask(MIPS16)
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Generate mips16 code
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@ -132,6 +148,10 @@ mmips-tfile
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Target
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Use the mips-tfile postpass
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mno-flush-func
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Target RejectNegative
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Do not use a cache-flushing function before calling stack trampolines
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mno-mips16
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Target Report RejectNegative InverseMask(MIPS16)
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Generate normal-mode code
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@ -160,6 +180,10 @@ msym32
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Target Report Var(TARGET_SYM32)
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Assume all symbols have 32-bit values
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mtune=
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Target RejectNegative Joined
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-mtune=PROCESSOR Optimize the output for PROCESSOR
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muninit-const-in-rodata
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Target Report Var(TARGET_UNINIT_CONST_IN_RODATA)
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Put uninitialized constants in ROM (needs -membedded-data)
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@ -1067,7 +1067,10 @@ compile_file (void)
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void
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display_target_options (void)
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{
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int undoc, i;
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int undoc;
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#if defined (TARGET_SWITCHES) || defined (TARGET_OPTIONS)
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int i;
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#endif
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unsigned int cli;
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static bool displayed = false;
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