Fix amdgcn issue with '0' constraints
2020-01-06 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for '0' matching inputs. (subv64di3_exec): Likewise. From-SVN: r279906
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@ -1,3 +1,9 @@
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2020-01-06 Andrew Stubbs <ams@codesourcery.com>
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* config/gcn/gcn-valu.md (subv64di3): Use separate alternatives for
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'0' matching inputs.
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(subv64di3_exec): Likewise.
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2020-01-06 Bryan Stenson <bryan@siliconvortex.com>
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* config/mips/mips.c (vr4130_align_insns): Fix typo.
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@ -1292,10 +1292,10 @@
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(set_attr "length" "8")])
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(define_insn_and_split "subv64di3"
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[(set (match_operand:V64DI 0 "register_operand" "= &v, &v")
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(minus:V64DI
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(match_operand:V64DI 1 "gcn_alu_operand" "vSvB0, v0")
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(match_operand:V64DI 2 "gcn_alu_operand" " v0,vSvB0")))
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[(set (match_operand:V64DI 0 "register_operand" "= &v, &v, &v, &v")
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(minus:V64DI
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(match_operand:V64DI 1 "gcn_alu_operand" "vSvB,vSvB0, v, v0")
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(match_operand:V64DI 2 "gcn_alu_operand" " v0, v,vSvB0,vSvB")))
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(clobber (reg:DI VCC_REG))]
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""
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"#"
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@ -1318,17 +1318,17 @@
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DONE;
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}
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[(set_attr "type" "vmult")
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(set_attr "length" "8,8")])
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(set_attr "length" "8")])
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(define_insn_and_split "subv64di3_exec"
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[(set (match_operand:V64DI 0 "register_operand" "= &v, &v")
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(vec_merge:V64DI
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(minus:V64DI
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(match_operand:V64DI 1 "gcn_alu_operand" "vSvB0, v0")
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(match_operand:V64DI 2 "gcn_alu_operand" " v0,vSvB0"))
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[(set (match_operand:V64DI 0 "register_operand" "= &v, &v, &v, &v")
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(vec_merge:V64DI
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(minus:V64DI
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(match_operand:V64DI 1 "gcn_alu_operand" "vSvB,vSvB0, v, v0")
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(match_operand:V64DI 2 "gcn_alu_operand" " v0, v,vSvB0,vSvB"))
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(match_operand:V64DI 3 "gcn_register_or_unspec_operand"
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" U0, U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" " e, e")))
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" U0, U0, U0, U0")
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(match_operand:DI 4 "gcn_exec_reg_operand" " e, e, e, e")))
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(clobber (reg:DI VCC_REG))]
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"register_operand (operands[1], VOIDmode)
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|| register_operand (operands[2], VOIDmode)"
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@ -1357,7 +1357,7 @@
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DONE;
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}
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[(set_attr "type" "vmult")
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(set_attr "length" "8,8")])
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(set_attr "length" "8")])
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(define_insn_and_split "addv64di3_dup"
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[(set (match_operand:V64DI 0 "register_operand" "= &v")
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