[ARM] Implement support for ACLE Coprocessor CDP intrinsics
gcc/ChangeLog: 2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/arm/arm.md (<cdp>): New. * config/arm/arm.c (neon_const_bounds): Rename this ... (arm_const_bounds): ... this. (arm_coproc_builtin_available): New. * config/arm/arm-builtins.c (SIMD_MAX_BUILTIN_ARGS): Increase. (arm_type_qualifiers): Add 'qualifier_unsigned_immediate'. (CDP_QUALIFIERS): Define to... (arm_cdp_qualifiers): ... this. New. (void_UP): Define. (arm_expand_builtin_args): Add case for 6 arguments. * config/arm/arm-protos.h (neon_const_bounds): Rename this ... (arm_const_bounds): ... this. (arm_coproc_builtin_available): New. * config/arm/arm_acle.h (__arm_cdp): New. (__arm_cdp2): New. * config/arm/arm_acle_builtins.def (cdp): New. (cdp2): New. * config/arm/iterators.md (CDPI,CDP,cdp): New. * config/arm/neon.md: Rename all 'neon_const_bounds' to 'arm_const_bounds'. * config/arm/types.md (coproc): New. * config/arm/unspecs.md (VUNSPEC_CDP, VUNSPEC_CDP2): New. * gcc/doc/extend.texi (ACLE): Add a mention of Coprocessor intrinsics. * gcc/doc/sourcebuild.texi (arm_coproc1_ok, arm_coproc2_ok, arm_coproc3_ok, arm_coproc4_ok): Document new effective targets. gcc/testsuite/ChangeLog: 2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com> * gcc.target/arm/acle/acle.exp: Run tests for different options and make sure fat-lto-objects is used such that we can still do assemble scans. * gcc.target/arm/acle/cdp.c: New. * gcc.target/arm/acle/cdp2.c: New. * lib/target-supports.exp (check_effective_target_arm_coproc1_ok): New. (check_effective_target_arm_coproc1_ok_nocache): New. (check_effective_target_arm_coproc2_ok): New. (check_effective_target_arm_coproc2_ok_nocache): New. (check_effective_target_arm_coproc3_ok): New. (check_effective_target_arm_coproc3_ok_nocache): New. (check_effective_target_arm_coproc4_ok): New. (check_effective_target_arm_coproc4_ok_nocache): New. From-SVN: r244172
This commit is contained in:
Andre Vieira
Andre Vieira
parent
7a2c8e28bd
commit
d57daa0c9d
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@ -1,3 +1,31 @@
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2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/arm/arm.md (<cdp>): New.
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* config/arm/arm.c (neon_const_bounds): Rename this ...
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(arm_const_bounds): ... this.
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(arm_coproc_builtin_available): New.
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* config/arm/arm-builtins.c (SIMD_MAX_BUILTIN_ARGS): Increase.
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(arm_type_qualifiers): Add 'qualifier_unsigned_immediate'.
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(CDP_QUALIFIERS): Define to...
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(arm_cdp_qualifiers): ... this. New.
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(void_UP): Define.
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(arm_expand_builtin_args): Add case for 6 arguments.
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* config/arm/arm-protos.h (neon_const_bounds): Rename this ...
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(arm_const_bounds): ... this.
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(arm_coproc_builtin_available): New.
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* config/arm/arm_acle.h (__arm_cdp): New.
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(__arm_cdp2): New.
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* config/arm/arm_acle_builtins.def (cdp): New.
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(cdp2): New.
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* config/arm/iterators.md (CDPI,CDP,cdp): New.
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* config/arm/neon.md: Rename all 'neon_const_bounds' to
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'arm_const_bounds'.
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* config/arm/types.md (coproc): New.
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* config/arm/unspecs.md (VUNSPEC_CDP, VUNSPEC_CDP2): New.
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* gcc/doc/extend.texi (ACLE): Add a mention of Coprocessor intrinsics.
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* gcc/doc/sourcebuild.texi (arm_coproc1_ok, arm_coproc2_ok,
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arm_coproc3_ok, arm_coproc4_ok): Document new effective targets.
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2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/arm/arm-builtins.c (arm_unsigned_binop_qualifiers): New.
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@ -39,7 +39,7 @@
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#include "case-cfn-macros.h"
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#include "sbitmap.h"
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#define SIMD_MAX_BUILTIN_ARGS 5
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#define SIMD_MAX_BUILTIN_ARGS 7
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enum arm_type_qualifiers
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{
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@ -54,6 +54,7 @@ enum arm_type_qualifiers
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/* Used when expanding arguments if an operand could
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be an immediate. */
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qualifier_immediate = 0x8, /* 1 << 3 */
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qualifier_unsigned_immediate = 0x9,
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qualifier_maybe_immediate = 0x10, /* 1 << 4 */
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/* void foo (...). */
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qualifier_void = 0x20, /* 1 << 5 */
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@ -165,6 +166,18 @@ arm_unsigned_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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qualifier_unsigned };
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#define UBINOP_QUALIFIERS (arm_unsigned_binop_qualifiers)
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/* void (unsigned immediate, unsigned immediate, unsigned immediate,
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unsigned immediate, unsigned immediate, unsigned immediate). */
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static enum arm_type_qualifiers
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arm_cdp_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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= { qualifier_void, qualifier_unsigned_immediate,
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qualifier_unsigned_immediate,
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qualifier_unsigned_immediate,
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qualifier_unsigned_immediate,
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qualifier_unsigned_immediate,
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qualifier_unsigned_immediate };
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#define CDP_QUALIFIERS \
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(arm_cdp_qualifiers)
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/* The first argument (return type) of a store should be void type,
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which we represent with qualifier_void. Their first operand will be
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a DImode pointer to the location to store to, so we must use
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@ -201,6 +214,7 @@ arm_storestruct_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
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#define oi_UP OImode
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#define hf_UP HFmode
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#define si_UP SImode
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#define void_UP VOIDmode
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#define UP(X) X##_UP
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@ -2226,6 +2240,10 @@ constant_arg:
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pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]);
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break;
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case 6:
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pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4], op[5]);
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break;
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default:
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gcc_unreachable ();
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}
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@ -2252,6 +2270,10 @@ constant_arg:
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pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
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break;
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case 6:
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pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]);
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break;
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default:
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gcc_unreachable ();
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}
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@ -96,7 +96,7 @@ extern rtx neon_make_constant (rtx);
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extern tree arm_builtin_vectorized_function (unsigned int, tree, tree);
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extern void neon_expand_vector_init (rtx, rtx);
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extern void neon_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
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extern void neon_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
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extern void arm_const_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
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extern HOST_WIDE_INT neon_element_bits (machine_mode);
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extern void neon_emit_pair_result_insn (machine_mode,
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rtx (*) (rtx, rtx, rtx, rtx),
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@ -176,6 +176,7 @@ extern void arm_expand_compare_and_swap (rtx op[]);
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extern void arm_split_compare_and_swap (rtx op[]);
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extern void arm_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
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extern rtx arm_load_tp (rtx);
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extern bool arm_coproc_builtin_available (enum unspecv);
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#if defined TREE_CODE
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extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
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@ -12206,7 +12206,7 @@ neon_lane_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high,
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/* Bounds-check constants. */
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void
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neon_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
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arm_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high)
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{
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bounds_check (operand, low, high, NULL_TREE, "constant");
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}
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@ -30888,4 +30888,34 @@ arm_expand_divmod_libfunc (rtx libfunc, machine_mode mode,
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*rem_p = remainder;
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}
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/* This function checks for the availability of the coprocessor builtin passed
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in BUILTIN for the current target. Returns true if it is available and
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false otherwise. If a BUILTIN is passed for which this function has not
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been implemented it will cause an exception. */
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bool
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arm_coproc_builtin_available (enum unspecv builtin)
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{
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/* None of these builtins are available in Thumb mode if the target only
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supports Thumb-1. */
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if (TARGET_THUMB1)
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return false;
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switch (builtin)
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{
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case VUNSPEC_CDP:
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if (arm_arch4)
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return true;
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break;
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case VUNSPEC_CDP2:
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/* Only present in ARMv5*, ARMv6 (but not ARMv6-M), ARMv7* and
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ARMv8-{A,M}. */
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if (arm_arch5)
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return true;
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break;
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default:
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gcc_unreachable ();
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}
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return false;
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}
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#include "gt-arm.h"
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@ -11919,6 +11919,26 @@
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DONE;
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})
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(define_insn "<cdp>"
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[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "n")
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(match_operand:SI 1 "immediate_operand" "n")
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(match_operand:SI 2 "immediate_operand" "n")
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(match_operand:SI 3 "immediate_operand" "n")
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(match_operand:SI 4 "immediate_operand" "n")
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(match_operand:SI 5 "immediate_operand" "n")] CDPI)]
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"arm_coproc_builtin_available (VUNSPEC_<CDP>)"
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{
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arm_const_bounds (operands[0], 0, 16);
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arm_const_bounds (operands[1], 0, 16);
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arm_const_bounds (operands[2], 0, (1 << 5));
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arm_const_bounds (operands[3], 0, (1 << 5));
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arm_const_bounds (operands[4], 0, (1 << 5));
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arm_const_bounds (operands[5], 0, 8);
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return "<cdp>\\tp%c0, %1, CR%c2, CR%c3, CR%c4, %5";
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}
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[(set_attr "length" "4")
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(set_attr "type" "coproc")])
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;; Vector bits common to IWMMXT and Neon
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(include "vec-common.md")
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;; Load the Intel Wireless Multimedia Extension patterns
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@ -32,6 +32,26 @@
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extern "C" {
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#endif
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#if (!__thumb__ || __thumb2__) && __ARM_ARCH >= 4
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_cdp (const unsigned int __coproc, const unsigned int __opc1,
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const unsigned int __CRd, const unsigned int __CRn,
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const unsigned int __CRm, const unsigned int __opc2)
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{
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return __builtin_arm_cdp (__coproc, __opc1, __CRd, __CRn, __CRm, __opc2);
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}
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#if __ARM_ARCH >= 5
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__arm_cdp2 (const unsigned int __coproc, const unsigned int __opc1,
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const unsigned int __CRd, const unsigned int __CRn,
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const unsigned int __CRm, const unsigned int __opc2)
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{
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return __builtin_arm_cdp2 (__coproc, __opc1, __CRd, __CRn, __CRm, __opc2);
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}
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#endif /* __ARM_ARCH >= 5. */
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#endif /* (!__thumb__ || __thumb2__) && __ARM_ARCH >= 4. */
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#ifdef __ARM_FEATURE_CRC32
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32b (uint32_t __a, uint8_t __b)
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@ -24,3 +24,5 @@ VAR1 (UBINOP, crc32w, si)
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VAR1 (UBINOP, crc32cb, si)
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VAR1 (UBINOP, crc32ch, si)
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VAR1 (UBINOP, crc32cw, si)
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VAR1 (CDP, cdp, void)
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VAR1 (CDP, cdp2, void)
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@ -943,3 +943,8 @@
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;; Attributes for VFMA_LANE/ VFMS_LANE
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(define_int_attr neon_vfm_lane_as
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[(UNSPEC_VFMA_LANE "a") (UNSPEC_VFMS_LANE "s")])
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;; An iterator for the CDP coprocessor instructions
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(define_int_iterator CDPI [VUNSPEC_CDP VUNSPEC_CDP2])
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(define_int_attr cdp [(VUNSPEC_CDP "cdp") (VUNSPEC_CDP2 "cdp2")])
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(define_int_attr CDP [(VUNSPEC_CDP "CDP") (VUNSPEC_CDP2 "CDP2")])
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@ -3654,7 +3654,7 @@ if (BYTES_BIG_ENDIAN)
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VCVT_US_N))]
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"TARGET_NEON"
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{
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neon_const_bounds (operands[2], 1, 33);
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arm_const_bounds (operands[2], 1, 33);
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return "vcvt.<sup>%#32.f32\t%<V_reg>0, %<V_reg>1, %2";
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}
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[(set_attr "type" "neon_fp_to_int_<V_elem_ch><q>")]
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@ -3668,7 +3668,7 @@ if (BYTES_BIG_ENDIAN)
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VCVT_US_N))]
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"TARGET_NEON_FP16INST"
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{
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neon_const_bounds (operands[2], 0, 17);
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arm_const_bounds (operands[2], 0, 17);
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return "vcvt.<sup>%#16.f16\t%<V_reg>0, %<V_reg>1, %2";
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}
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[(set_attr "type" "neon_fp_to_int_<VH_elem_ch><q>")]
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@ -3681,7 +3681,7 @@ if (BYTES_BIG_ENDIAN)
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VCVT_US_N))]
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"TARGET_NEON"
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{
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neon_const_bounds (operands[2], 1, 33);
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arm_const_bounds (operands[2], 1, 33);
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return "vcvt.f32.<sup>%#32\t%<V_reg>0, %<V_reg>1, %2";
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}
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[(set_attr "type" "neon_int_to_fp_<V_elem_ch><q>")]
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@ -3695,7 +3695,7 @@ if (BYTES_BIG_ENDIAN)
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VCVT_US_N))]
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"TARGET_NEON_FP16INST"
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{
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neon_const_bounds (operands[2], 0, 17);
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arm_const_bounds (operands[2], 0, 17);
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return "vcvt.f16.<sup>%#16\t%<V_reg>0, %<V_reg>1, %2";
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}
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[(set_attr "type" "neon_int_to_fp_<VH_elem_ch><q>")]
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@ -4300,7 +4300,7 @@ if (BYTES_BIG_ENDIAN)
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UNSPEC_VEXT))]
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"TARGET_NEON"
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{
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neon_const_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
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arm_const_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
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return "vext.<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2, %3";
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}
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[(set_attr "type" "neon_ext<q>")]
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@ -4397,7 +4397,7 @@ if (BYTES_BIG_ENDIAN)
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VSHR_N))]
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"TARGET_NEON"
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{
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neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) + 1);
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arm_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) + 1);
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return "v<shift_op>.<sup>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %2";
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}
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[(set_attr "type" "neon_shift_imm<q>")]
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@ -4411,7 +4411,7 @@ if (BYTES_BIG_ENDIAN)
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VSHRN_N))]
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"TARGET_NEON"
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{
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neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
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arm_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
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return "v<shift_op>.<V_if_elem>\t%P0, %q1, %2";
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}
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[(set_attr "type" "neon_shift_imm_narrow_q")]
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@ -4425,7 +4425,7 @@ if (BYTES_BIG_ENDIAN)
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VQSHRN_N))]
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"TARGET_NEON"
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{
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neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
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arm_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
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return "v<shift_op>.<sup>%#<V_sz_elem>\t%P0, %q1, %2";
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}
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[(set_attr "type" "neon_sat_shift_imm_narrow_q")]
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@ -4439,7 +4439,7 @@ if (BYTES_BIG_ENDIAN)
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VQSHRUN_N))]
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"TARGET_NEON"
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{
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neon_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
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arm_const_bounds (operands[2], 1, neon_element_bits (<MODE>mode) / 2 + 1);
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return "v<shift_op>.<V_s_elem>\t%P0, %q1, %2";
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}
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[(set_attr "type" "neon_sat_shift_imm_narrow_q")]
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@ -4452,7 +4452,7 @@ if (BYTES_BIG_ENDIAN)
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UNSPEC_VSHL_N))]
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"TARGET_NEON"
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{
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neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
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arm_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
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return "vshl.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %2";
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}
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[(set_attr "type" "neon_shift_imm<q>")]
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@ -4465,7 +4465,7 @@ if (BYTES_BIG_ENDIAN)
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VQSHL_N))]
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"TARGET_NEON"
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{
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||||
neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
|
||||
arm_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
|
||||
return "vqshl.<sup>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %2";
|
||||
}
|
||||
[(set_attr "type" "neon_sat_shift_imm<q>")]
|
||||
|
|
@ -4478,7 +4478,7 @@ if (BYTES_BIG_ENDIAN)
|
|||
UNSPEC_VQSHLU_N))]
|
||||
"TARGET_NEON"
|
||||
{
|
||||
neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
|
||||
arm_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode));
|
||||
return "vqshlu.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %2";
|
||||
}
|
||||
[(set_attr "type" "neon_sat_shift_imm<q>")]
|
||||
|
|
@ -4492,7 +4492,7 @@ if (BYTES_BIG_ENDIAN)
|
|||
"TARGET_NEON"
|
||||
{
|
||||
/* The boundaries are: 0 < imm <= size. */
|
||||
neon_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode) + 1);
|
||||
arm_const_bounds (operands[2], 0, neon_element_bits (<MODE>mode) + 1);
|
||||
return "vshll.<sup>%#<V_sz_elem>\t%q0, %P1, %2";
|
||||
}
|
||||
[(set_attr "type" "neon_shift_imm_long")]
|
||||
|
|
@ -4507,7 +4507,7 @@ if (BYTES_BIG_ENDIAN)
|
|||
VSRA_N))]
|
||||
"TARGET_NEON"
|
||||
{
|
||||
neon_const_bounds (operands[3], 1, neon_element_bits (<MODE>mode) + 1);
|
||||
arm_const_bounds (operands[3], 1, neon_element_bits (<MODE>mode) + 1);
|
||||
return "v<shift_op>.<sup>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
|
||||
}
|
||||
[(set_attr "type" "neon_shift_acc<q>")]
|
||||
|
|
@ -4521,7 +4521,7 @@ if (BYTES_BIG_ENDIAN)
|
|||
UNSPEC_VSRI))]
|
||||
"TARGET_NEON"
|
||||
{
|
||||
neon_const_bounds (operands[3], 1, neon_element_bits (<MODE>mode) + 1);
|
||||
arm_const_bounds (operands[3], 1, neon_element_bits (<MODE>mode) + 1);
|
||||
return "vsri.<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
|
||||
}
|
||||
[(set_attr "type" "neon_shift_reg<q>")]
|
||||
|
|
@ -4535,7 +4535,7 @@ if (BYTES_BIG_ENDIAN)
|
|||
UNSPEC_VSLI))]
|
||||
"TARGET_NEON"
|
||||
{
|
||||
neon_const_bounds (operands[3], 0, neon_element_bits (<MODE>mode));
|
||||
arm_const_bounds (operands[3], 0, neon_element_bits (<MODE>mode));
|
||||
return "vsli.<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
|
||||
}
|
||||
[(set_attr "type" "neon_shift_reg<q>")]
|
||||
|
|
|
|||
|
|
@ -539,6 +539,10 @@
|
|||
; crypto_sha1_slow
|
||||
; crypto_sha256_fast
|
||||
; crypto_sha256_slow
|
||||
;
|
||||
; The classification below is for coprocessor instructions
|
||||
;
|
||||
; coproc
|
||||
|
||||
(define_attr "type"
|
||||
"adc_imm,\
|
||||
|
|
@ -1073,7 +1077,8 @@
|
|||
crypto_sha1_fast,\
|
||||
crypto_sha1_slow,\
|
||||
crypto_sha256_fast,\
|
||||
crypto_sha256_slow"
|
||||
crypto_sha256_slow,\
|
||||
coproc"
|
||||
(const_string "untyped"))
|
||||
|
||||
; Is this an (integer side) multiply with a 32-bit (or smaller) result?
|
||||
|
|
|
|||
|
|
@ -150,6 +150,8 @@
|
|||
VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content.
|
||||
VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content.
|
||||
VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing.
|
||||
VUNSPEC_CDP ; Represent the coprocessor cdp instruction.
|
||||
VUNSPEC_CDP2 ; Represent the coprocessor cdp2 instruction.
|
||||
])
|
||||
|
||||
;; Enumerators for NEON unspecs.
|
||||
|
|
|
|||
|
|
@ -1886,7 +1886,7 @@
|
|||
(float_truncate:HF (float:SF (match_dup 0))))]
|
||||
"TARGET_VFP_FP16INST"
|
||||
{
|
||||
neon_const_bounds (operands[2], 1, 33);
|
||||
arm_const_bounds (operands[2], 1, 33);
|
||||
return "vcvt.f16.<sup>32\t%0, %0, %2\;vmov.f32\t%3, %0";
|
||||
}
|
||||
[(set_attr "conds" "unconditional")
|
||||
|
|
@ -1903,7 +1903,7 @@
|
|||
{
|
||||
rtx op1 = gen_reg_rtx (SImode);
|
||||
|
||||
neon_const_bounds (operands[2], 1, 33);
|
||||
arm_const_bounds (operands[2], 1, 33);
|
||||
|
||||
emit_move_insn (op1, operands[1]);
|
||||
emit_insn (gen_neon_vcvth<sup>_nhf_unspec (op1, op1, operands[2],
|
||||
|
|
@ -1927,7 +1927,7 @@
|
|||
VCVT_SI_US_N))]
|
||||
"TARGET_VFP_FP16INST"
|
||||
{
|
||||
neon_const_bounds (operands[2], 1, 33);
|
||||
arm_const_bounds (operands[2], 1, 33);
|
||||
return "vmov.f32\t%0, %1\;vcvt.<sup>%#32.f16\t%0, %0, %2";
|
||||
}
|
||||
[(set_attr "conds" "unconditional")
|
||||
|
|
@ -1945,7 +1945,7 @@
|
|||
{
|
||||
rtx op1 = gen_reg_rtx (SImode);
|
||||
|
||||
neon_const_bounds (operands[2], 1, 33);
|
||||
arm_const_bounds (operands[2], 1, 33);
|
||||
emit_insn (gen_neon_vcvth<sup>_nsi_unspec (op1, operands[1], operands[2]));
|
||||
emit_move_insn (operands[0], op1);
|
||||
DONE;
|
||||
|
|
|
|||
|
|
@ -12625,8 +12625,9 @@ The built-in intrinsics for the Advanced SIMD extension are available when
|
|||
NEON is enabled.
|
||||
|
||||
Currently, ARM and AArch64 back ends do not support ACLE 2.0 fully. Both
|
||||
back ends support CRC32 intrinsics from @file{arm_acle.h}. The ARM back end's
|
||||
16-bit floating-point Advanced SIMD intrinsics currently comply to ACLE v1.1.
|
||||
back ends support CRC32 intrinsics and the ARM back end supports the
|
||||
Coprocessor intrinsics, all from @file{arm_acle.h}. The ARM back end's 16-bit
|
||||
floating-point Advanced SIMD intrinsics currently comply to ACLE v1.1.
|
||||
AArch64's back end does not have support for 16-bit floating point Advanced SIMD
|
||||
intrinsics yet.
|
||||
|
||||
|
|
|
|||
|
|
@ -1678,6 +1678,25 @@ div instruction.
|
|||
ARM target supports ARMv8-M Security Extensions, enabled by the @code{-mcmse}
|
||||
option.
|
||||
|
||||
@item arm_coproc1_ok
|
||||
@anchor{arm_coproc1_ok}
|
||||
ARM target supports the following coprocessor instructions: @code{CDP},
|
||||
@code{LDC}, @code{STC}, @code{MCR} and @code{MRC}.
|
||||
|
||||
@item arm_coproc2_ok
|
||||
@anchor{arm_coproc2_ok}
|
||||
ARM target supports all the coprocessor instructions also listed as supported
|
||||
in @ref{arm_coproc1_ok} in addition to the following: @code{CDP2}, @code{LDC2},
|
||||
@code{LDC2l}, @code{STC2}, @code{STC2l}, @code{MCR2} and @code{MRC2}.
|
||||
|
||||
@item arm_coproc3_ok
|
||||
@anchor{arm_coproc3_ok}
|
||||
ARM target supports all the coprocessor instructions also listed as supported
|
||||
in @ref{arm_coproc2_ok} in addition the following: @code{MCRR} and @code{MRRC}.
|
||||
|
||||
@item arm_coproc4_ok
|
||||
ARM target supports all the coprocessor instructions also listed as supported
|
||||
in @ref{arm_coproc3_ok} in addition the following: @code{MCRR2} and @code{MRRC2}.
|
||||
@end table
|
||||
|
||||
@subsubsection AArch64-specific attributes
|
||||
|
|
|
|||
|
|
@ -1,3 +1,19 @@
|
|||
2017-01-06 Andre Vieira <andre.simoesdiasvieira@arm.com>
|
||||
|
||||
* gcc.target/arm/acle/acle.exp: Run tests for different options
|
||||
and make sure fat-lto-objects is used such that we can still do
|
||||
assemble scans.
|
||||
* gcc.target/arm/acle/cdp.c: New.
|
||||
* gcc.target/arm/acle/cdp2.c: New.
|
||||
* lib/target-supports.exp (check_effective_target_arm_coproc1_ok): New.
|
||||
(check_effective_target_arm_coproc1_ok_nocache): New.
|
||||
(check_effective_target_arm_coproc2_ok): New.
|
||||
(check_effective_target_arm_coproc2_ok_nocache): New.
|
||||
(check_effective_target_arm_coproc3_ok): New.
|
||||
(check_effective_target_arm_coproc3_ok_nocache): New.
|
||||
(check_effective_target_arm_coproc4_ok): New.
|
||||
(check_effective_target_arm_coproc4_ok_nocache): New.
|
||||
|
||||
2017-01-06 Martin Sebor <msebor@redhat.com>
|
||||
|
||||
PR middle-end/78605
|
||||
|
|
|
|||
|
|
@ -27,9 +27,26 @@ load_lib gcc-dg.exp
|
|||
# Initialize `dg'.
|
||||
dg-init
|
||||
|
||||
set saved-dg-do-what-default ${dg-do-what-default}
|
||||
set dg-do-what-default "assemble"
|
||||
|
||||
set saved-lto_torture_options ${LTO_TORTURE_OPTIONS}
|
||||
|
||||
# Add -ffat-lto-objects option to all LTO options such that we can do assembly
|
||||
# scans.
|
||||
proc add_fat_objects { list } {
|
||||
set res {}
|
||||
foreach el $list {set res [lappend res [concat $el " -ffat-lto-objects"]]}
|
||||
return $res
|
||||
};
|
||||
set LTO_TORTURE_OPTIONS [add_fat_objects ${LTO_TORTURE_OPTIONS}]
|
||||
|
||||
# Main loop.
|
||||
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
|
||||
gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
|
||||
"" ""
|
||||
|
||||
# Restore globals
|
||||
set dg-do-what-default ${saved-dg-do-what-default}
|
||||
set LTO_TORTURE_OPTIONS ${saved-lto_torture_options}
|
||||
# All done.
|
||||
dg-finish
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
/* Test the cdp ACLE intrinsic. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-save-temps" } */
|
||||
/* { dg-require-effective-target arm_coproc1_ok } */
|
||||
|
||||
#include "arm_acle.h"
|
||||
|
||||
void test_cdp (void)
|
||||
{
|
||||
__arm_cdp (10, 1, 2, 3, 4, 5);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "cdp\tp10, #1, CR2, CR3, CR4, #5\n" } } */
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/* Test the cdp2 ACLE intrinsic. */
|
||||
|
||||
/* { dg-do assemble } */
|
||||
/* { dg-options "-save-temps" } */
|
||||
/* { dg-require-effective-target arm_coproc2_ok } */
|
||||
|
||||
#include "arm_acle.h"
|
||||
|
||||
void test_cdp2 (void)
|
||||
{
|
||||
__arm_cdp2 (10, 4, 3, 2, 1, 0);
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "cdp2\tp10, #4, CR3, CR2, CR1, #0\n" } } */
|
||||
|
|
@ -8239,3 +8239,78 @@ proc check_effective_target_store_merge { } {
|
|||
|
||||
return 0
|
||||
}
|
||||
|
||||
# Return 1 if the target supports coprocessor instructions: cdp, ldc, stc, mcr and
|
||||
# mrc.
|
||||
proc check_effective_target_arm_coproc1_ok_nocache { } {
|
||||
if { ![istarget arm*-*-*] } {
|
||||
return 0
|
||||
}
|
||||
return [check_no_compiler_messages_nocache arm_coproc1_ok assembly {
|
||||
#if (__thumb__ && !__thumb2__) || __ARM_ARCH < 4
|
||||
#error FOO
|
||||
#endif
|
||||
}]
|
||||
}
|
||||
|
||||
proc check_effective_target_arm_coproc1_ok { } {
|
||||
return [check_cached_effective_target arm_coproc1_ok \
|
||||
check_effective_target_arm_coproc1_ok_nocache]
|
||||
}
|
||||
|
||||
# Return 1 if the target supports all coprocessor instructions checked by
|
||||
# check_effective_target_arm_coproc1_ok in addition to the following: cdp2,
|
||||
# ldc2, ldc2l, stc2, stc2l, mcr2 and mrc2.
|
||||
proc check_effective_target_arm_coproc2_ok_nocache { } {
|
||||
if { ![check_effective_target_arm_coproc1_ok] } {
|
||||
return 0
|
||||
}
|
||||
return [check_no_compiler_messages_nocache arm_coproc2_ok assembly {
|
||||
#if __ARM_ARCH < 5
|
||||
#error FOO
|
||||
#endif
|
||||
}]
|
||||
}
|
||||
|
||||
proc check_effective_target_arm_coproc2_ok { } {
|
||||
return [check_cached_effective_target arm_coproc2_ok \
|
||||
check_effective_target_arm_coproc2_ok_nocache]
|
||||
}
|
||||
|
||||
# Return 1 if the target supports all coprocessor instructions checked by
|
||||
# check_effective_target_arm_coproc2_ok in addition the following: mcrr and
|
||||
mrrc.
|
||||
proc check_effective_target_arm_coproc3_ok_nocache { } {
|
||||
if { ![check_effective_target_arm_coproc2_ok] } {
|
||||
return 0
|
||||
}
|
||||
return [check_no_compiler_messages_nocache arm_coproc3_ok assembly {
|
||||
#if __ARM_ARCH < 6 && !defined (__ARM_ARCH_5TE__)
|
||||
#error FOO
|
||||
#endif
|
||||
}]
|
||||
}
|
||||
|
||||
proc check_effective_target_arm_coproc3_ok { } {
|
||||
return [check_cached_effective_target arm_coproc3_ok \
|
||||
check_effective_target_arm_coproc3_ok_nocache]
|
||||
}
|
||||
|
||||
# Return 1 if the target supports all coprocessor instructions checked by
|
||||
# check_effective_target_arm_coproc3_ok in addition the following: mcrr2 and
|
||||
# mrcc2.
|
||||
proc check_effective_target_arm_coproc4_ok_nocache { } {
|
||||
if { ![check_effective_target_arm_coproc3_ok] } {
|
||||
return 0
|
||||
}
|
||||
return [check_no_compiler_messages_nocache arm_coproc4_ok assembly {
|
||||
#if __ARM_ARCH < 6
|
||||
#error FOO
|
||||
#endif
|
||||
}]
|
||||
}
|
||||
|
||||
proc check_effective_target_arm_coproc4_ok { } {
|
||||
return [check_cached_effective_target arm_coproc4_ok \
|
||||
check_effective_target_arm_coproc4_ok_nocache]
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue