i386: Use xor to write zero to memory with -Os even for more than 4 stores [PR11877]
> > 2021-06-20 Roger Sayle <roger@nextmovesoftware.com> > > > > gcc/ChangeLog > > PR target/11877 > > * config/i386/i386.md: New define_peephole2s to shrink writing > > 1, 2 or 4 consecutive zeros to memory when optimizing for size. It unfortunately doesn't extend well to larger memory clearing. Consider e.g. void foo (int *p) { p[0] = 0; p[7] = 0; p[23] = 0; p[41] = 0; p[48] = 0; p[59] = 0; p[69] = 0; p[78] = 0; p[83] = 0; p[89] = 0; p[98] = 0; p[121] = 0; p[132] = 0; p[143] = 0; p[154] = 0; } where with the patch we emit: xorl %eax, %eax xorl %edx, %edx xorl %ecx, %ecx xorl %esi, %esi xorl %r8d, %r8d movl %eax, (%rdi) movl %eax, 28(%rdi) movl %eax, 92(%rdi) movl %eax, 164(%rdi) movl %edx, 192(%rdi) movl %edx, 236(%rdi) movl %edx, 276(%rdi) movl %edx, 312(%rdi) movl %ecx, 332(%rdi) movl %ecx, 356(%rdi) movl %ecx, 392(%rdi) movl %ecx, 484(%rdi) movl %esi, 528(%rdi) movl %esi, 572(%rdi) movl %r8d, 616(%rdi) Here is an incremental patch that emits: xorl %eax, %eax movl %eax, (%rdi) movl %eax, 28(%rdi) movl %eax, 92(%rdi) movl %eax, 164(%rdi) movl %eax, 192(%rdi) movl %eax, 236(%rdi) movl %eax, 276(%rdi) movl %eax, 312(%rdi) movl %eax, 332(%rdi) movl %eax, 356(%rdi) movl %eax, 392(%rdi) movl %eax, 484(%rdi) movl %eax, 528(%rdi) movl %eax, 572(%rdi) movl %eax, 616(%rdi) instead. 2021-06-22 Jakub Jelinek <jakub@redhat.com> PR target/11877 * config/i386/i386-protos.h (ix86_last_zero_store_uid): Declare. * config/i386/i386-expand.c (ix86_last_zero_store_uid): New variable. * config/i386/i386.c (ix86_expand_prologue): Clear it. * config/i386/i386.md (peephole2s for 1/2/4 stores of const0_rtx): Remove "" from match_operand. Emit new insns using emit_move_insn and set ix86_last_zero_store_uid to INSN_UID of the last store. Add peephole2s for 1/2/4 stores of const0_rtx following previous successful peep2s. * gcc.target/i386/pr11877-2.c: New test.
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@ -1316,6 +1316,9 @@ find_nearest_reg_def (rtx_insn *insn, int regno1, int regno2)
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return false;
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}
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/* INSN_UID of the last insn emitted by zero store peephole2s. */
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int ix86_last_zero_store_uid;
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/* Split lea instructions into a sequence of instructions
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which are executed on ALU to avoid AGU stalls.
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It is assumed that it is allowed to clobber flags register
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@ -111,6 +111,7 @@ extern bool ix86_use_lea_for_mov (rtx_insn *, rtx[]);
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extern bool ix86_avoid_lea_for_addr (rtx_insn *, rtx[]);
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extern void ix86_split_lea_for_addr (rtx_insn *, rtx[], machine_mode);
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extern bool ix86_lea_for_add_ok (rtx_insn *, rtx[]);
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extern int ix86_last_zero_store_uid;
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extern bool ix86_vec_interleave_v2df_operator_ok (rtx operands[3], bool high);
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extern bool ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn);
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extern bool ix86_agi_dependent (rtx_insn *set_insn, rtx_insn *use_insn);
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@ -8196,6 +8196,7 @@ ix86_expand_prologue (void)
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bool save_stub_call_needed;
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rtx static_chain = NULL_RTX;
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ix86_last_zero_store_uid = 0;
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if (ix86_function_naked (current_function_decl))
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{
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if (flag_stack_usage_info)
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@ -19360,37 +19360,96 @@
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;; When optimizing for size, zeroing memory should use a register.
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(define_peephole2
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[(match_scratch:SWI48 0 "r")
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(set (match_operand:SWI48 1 "memory_operand" "") (const_int 0))
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(set (match_operand:SWI48 2 "memory_operand" "") (const_int 0))
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(set (match_operand:SWI48 3 "memory_operand" "") (const_int 0))
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(set (match_operand:SWI48 4 "memory_operand" "") (const_int 0))]
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(set (match_operand:SWI48 1 "memory_operand") (const_int 0))
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(set (match_operand:SWI48 2 "memory_operand") (const_int 0))
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(set (match_operand:SWI48 3 "memory_operand") (const_int 0))
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(set (match_operand:SWI48 4 "memory_operand") (const_int 0))]
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"optimize_insn_for_size_p () && peep2_regno_dead_p (0, FLAGS_REG)"
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[(set (match_dup 1) (match_dup 0))
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(set (match_dup 2) (match_dup 0))
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(set (match_dup 3) (match_dup 0))
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(set (match_dup 4) (match_dup 0))]
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[(const_int 0)]
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{
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ix86_expand_clear (operands[0]);
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emit_move_insn (operands[1], operands[0]);
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emit_move_insn (operands[2], operands[0]);
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emit_move_insn (operands[3], operands[0]);
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ix86_last_zero_store_uid
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= INSN_UID (emit_move_insn (operands[4], operands[0]));
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DONE;
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})
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(define_peephole2
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[(match_scratch:SWI48 0 "r")
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(set (match_operand:SWI48 1 "memory_operand" "") (const_int 0))
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(set (match_operand:SWI48 2 "memory_operand" "") (const_int 0))]
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(set (match_operand:SWI48 1 "memory_operand") (const_int 0))
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(set (match_operand:SWI48 2 "memory_operand") (const_int 0))]
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"optimize_insn_for_size_p () && peep2_regno_dead_p (0, FLAGS_REG)"
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[(set (match_dup 1) (match_dup 0))
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(set (match_dup 2) (match_dup 0))]
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[(const_int 0)]
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{
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ix86_expand_clear (operands[0]);
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emit_move_insn (operands[1], operands[0]);
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ix86_last_zero_store_uid
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= INSN_UID (emit_move_insn (operands[2], operands[0]));
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DONE;
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})
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(define_peephole2
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[(match_scratch:SWI48 0 "r")
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(set (match_operand:SWI48 1 "memory_operand" "") (const_int 0))]
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(set (match_operand:SWI48 1 "memory_operand") (const_int 0))]
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"optimize_insn_for_size_p () && peep2_regno_dead_p (0, FLAGS_REG)"
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[(set (match_dup 1) (match_dup 0))]
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[(const_int 0)]
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{
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ix86_expand_clear (operands[0]);
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ix86_last_zero_store_uid
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= INSN_UID (emit_move_insn (operands[1], operands[0]));
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DONE;
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})
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(define_peephole2
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[(set (match_operand:SWI48 5 "memory_operand")
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(match_operand:SWI48 0 "general_reg_operand"))
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(set (match_operand:SWI48 1 "memory_operand") (const_int 0))
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(set (match_operand:SWI48 2 "memory_operand") (const_int 0))
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(set (match_operand:SWI48 3 "memory_operand") (const_int 0))
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(set (match_operand:SWI48 4 "memory_operand") (const_int 0))]
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"optimize_insn_for_size_p ()
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&& INSN_UID (peep2_next_insn (0)) == ix86_last_zero_store_uid"
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[(const_int 0)]
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{
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emit_move_insn (operands[5], operands[0]);
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emit_move_insn (operands[1], operands[0]);
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emit_move_insn (operands[2], operands[0]);
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emit_move_insn (operands[3], operands[0]);
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ix86_last_zero_store_uid
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= INSN_UID (emit_move_insn (operands[4], operands[0]));
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DONE;
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})
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(define_peephole2
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[(set (match_operand:SWI48 3 "memory_operand")
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(match_operand:SWI48 0 "general_reg_operand"))
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(set (match_operand:SWI48 1 "memory_operand") (const_int 0))
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(set (match_operand:SWI48 2 "memory_operand") (const_int 0))]
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"optimize_insn_for_size_p ()
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&& INSN_UID (peep2_next_insn (0)) == ix86_last_zero_store_uid"
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[(const_int 0)]
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{
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emit_move_insn (operands[3], operands[0]);
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emit_move_insn (operands[1], operands[0]);
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ix86_last_zero_store_uid
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= INSN_UID (emit_move_insn (operands[2], operands[0]));
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DONE;
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})
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(define_peephole2
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[(set (match_operand:SWI48 2 "memory_operand")
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(match_operand:SWI48 0 "general_reg_operand"))
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(set (match_operand:SWI48 1 "memory_operand") (const_int 0))]
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"optimize_insn_for_size_p ()
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&& INSN_UID (peep2_next_insn (0)) == ix86_last_zero_store_uid"
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[(const_int 0)]
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{
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emit_move_insn (operands[2], operands[0]);
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ix86_last_zero_store_uid
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= INSN_UID (emit_move_insn (operands[1], operands[0]));
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DONE;
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})
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;; Reload dislikes loading constants directly into class_likely_spilled
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26
gcc/testsuite/gcc.target/i386/pr11877-2.c
Normal file
26
gcc/testsuite/gcc.target/i386/pr11877-2.c
Normal file
@ -0,0 +1,26 @@
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/* PR target/11877 */
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/* { dg-do compile } */
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/* { dg-options "-Os" } */
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void
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foo (int *p)
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{
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p[0] = 0;
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p[7] = 0;
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p[23] = 0;
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p[41] = 0;
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p[48] = 0;
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p[59] = 0;
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p[69] = 0;
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p[78] = 0;
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p[83] = 0;
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p[89] = 0;
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p[98] = 0;
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p[121] = 0;
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p[132] = 0;
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p[143] = 0;
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p[154] = 0;
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}
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/* { dg-final { scan-assembler-times "xorl\[ \t\]" 1 } } */
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/* { dg-final { scan-assembler-not "\\\$0," } } */
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