i386.h (SSE_VEC_FLOAT_MODE_P): New define.
* config/i386/i386.h (SSE_VEC_FLOAT_MODE_P): New define. * config/i386/i386.md (*sse_setcc<mode>): Macroize from *sse_setccsf and *sse_setccdf using MODEF mode iterator and SSE_FLOAT_MODE_P as insn constraint. (smin<mode>3): Ditto from similar patterns. (smax<mode>3): Ditto. (*ieee_smin<mode>3): Ditto. (*ieee_smax<mode>3): Ditto. * config/i386/sse.md (sse): New mode attribute. (mov<mode>): Macroize expander from movv4sf and movv2df using SSEMODEF2P mode iterator. (<sse>_movnt<mode>): Ditto from similar patterns. Use SSE_VEC_FLOAT_MODE_P as insn constraint. (storent<mode>): Ditto. (storent<mode>): Macroize expander from storentsf and storentdf using MODEF mode iterator. (neg<mode>2): Macroize from negv4sf2 and negv2df2 using SSEMODEF2P mode iterator and SSE_VEC_FLOAT_MODE_P as insn constraint. (abs<mode>2): Ditto from similar patterns. (add<mode>3, *add<mode>3, <sse>_vmadd<mode>3): Ditto. (sub<mode>3, *sub<mode>3, <sse>_vmsub<mode>3): Ditto. (<sse>_div<mode>3, <sse>_vmdiv<mode>3): Ditto. (<sse>_vmsqrt<mode>2): Ditto. (smin<mode>3, *smin<mode>3_finite, *smin<mode>3) (<sse>_vmsmin<mode>3, *ieee_smin<mode>3): Ditto. (smax<mode>3, *smax<mode>3_finite, *smax<mode>3) (<sse>_vmsmax<mode>3, *ieee_smax<mode>3): Ditto. (<sse>_maskcmp<mode>3): Macroize from sse_maskcmpv4sf3, sse_maskcmpsf3, sse2_maskcmpv2df3 and sse2_maskcmpdf3 using SSEMODEF4 mode iterator. Use SSE_FLOAT_MODE_P with SSE_VEC_FLOAT_MODE_P as insn constraint. (<sse>_comi): Macroize from sse_comi and sse2_comi using MODEF mode iterator and SSE_FLOAT_MODE_P as insn constraint. (<sse>_ucomi): Ditto from similar patterns. (<sse>_vmmaskcmp<mode>3): Macroize from sse_vmmaskcmpv4sf3 and sse2_vmmaskcmpv2df3 using SSEMODEF2P mode iterator and SSE_VEC_FLOAT_MODE_P as insn constraint. (vcond<mode>): Ditto from similar patterns. (and<mode>3, *and<mode>3): Ditto. (<sse>_nand<mode>3): Ditto. (ior<mode>3, *ior<mode>3): Ditto. (xor<mode>3, *xor<mode>3): Ditto. (*and<mode>3): Macroize from *andsf3 and *anddf3 using MODEF mode iterator and SSE_FLOAT_MODE_P as insn constraint. (*nand<mode>3): Ditto from similar patterns. (*ior<mode>3): Ditto. (*xor<mode>3): Ditto. From-SVN: r132478
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
57a65098f6
commit
d6023b50b7
@ -1,3 +1,53 @@
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2008-02-20 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.h (SSE_VEC_FLOAT_MODE_P): New define.
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* config/i386/i386.md (*sse_setcc<mode>): Macroize from *sse_setccsf
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and *sse_setccdf using MODEF mode iterator and SSE_FLOAT_MODE_P as
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insn constraint.
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(smin<mode>3): Ditto from similar patterns.
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(smax<mode>3): Ditto.
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(*ieee_smin<mode>3): Ditto.
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(*ieee_smax<mode>3): Ditto.
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* config/i386/sse.md (sse): New mode attribute.
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(mov<mode>): Macroize expander from movv4sf and movv2df using
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SSEMODEF2P mode iterator.
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(<sse>_movnt<mode>): Ditto from similar patterns. Use
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SSE_VEC_FLOAT_MODE_P as insn constraint.
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(storent<mode>): Ditto.
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(storent<mode>): Macroize expander from storentsf and storentdf using
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MODEF mode iterator.
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(neg<mode>2): Macroize from negv4sf2 and negv2df2 using SSEMODEF2P
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mode iterator and SSE_VEC_FLOAT_MODE_P as insn constraint.
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(abs<mode>2): Ditto from similar patterns.
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(add<mode>3, *add<mode>3, <sse>_vmadd<mode>3): Ditto.
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(sub<mode>3, *sub<mode>3, <sse>_vmsub<mode>3): Ditto.
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(<sse>_div<mode>3, <sse>_vmdiv<mode>3): Ditto.
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(<sse>_vmsqrt<mode>2): Ditto.
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(smin<mode>3, *smin<mode>3_finite, *smin<mode>3)
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(<sse>_vmsmin<mode>3, *ieee_smin<mode>3): Ditto.
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(smax<mode>3, *smax<mode>3_finite, *smax<mode>3)
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(<sse>_vmsmax<mode>3, *ieee_smax<mode>3): Ditto.
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(<sse>_maskcmp<mode>3): Macroize from sse_maskcmpv4sf3,
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sse_maskcmpsf3, sse2_maskcmpv2df3 and sse2_maskcmpdf3 using SSEMODEF4
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mode iterator. Use SSE_FLOAT_MODE_P with SSE_VEC_FLOAT_MODE_P as
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insn constraint.
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(<sse>_comi): Macroize from sse_comi and sse2_comi using MODEF mode
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iterator and SSE_FLOAT_MODE_P as insn constraint.
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(<sse>_ucomi): Ditto from similar patterns.
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(<sse>_vmmaskcmp<mode>3): Macroize from sse_vmmaskcmpv4sf3 and
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sse2_vmmaskcmpv2df3 using SSEMODEF2P mode iterator and
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SSE_VEC_FLOAT_MODE_P as insn constraint.
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(vcond<mode>): Ditto from similar patterns.
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(and<mode>3, *and<mode>3): Ditto.
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(<sse>_nand<mode>3): Ditto.
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(ior<mode>3, *ior<mode>3): Ditto.
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(xor<mode>3, *xor<mode>3): Ditto.
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(*and<mode>3): Macroize from *andsf3 and *anddf3 using MODEF mode
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iterator and SSE_FLOAT_MODE_P as insn constraint.
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(*nand<mode>3): Ditto from similar patterns.
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(*ior<mode>3): Ditto.
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(*xor<mode>3): Ditto.
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2008-02-20 Ira Rosen <irar@il.ibm.com>
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* config/spu/spu.md (vec_unpacku_hi_v8hi, vec_unpacku_lo_v8hi,
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@ -1454,6 +1454,9 @@ enum reg_class
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#define SSE_FLOAT_MODE_P(MODE) \
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((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode))
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#define SSE_VEC_FLOAT_MODE_P(MODE) \
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((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode))
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#define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP)))
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#define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG)
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@ -13964,25 +13964,15 @@
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;; 0xffffffff is NaN, but not in normalized form, so we can't represent
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;; it directly.
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(define_insn "*sse_setccsf"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(match_operator:SF 1 "sse_comparison_operator"
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[(match_operand:SF 2 "register_operand" "0")
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(match_operand:SF 3 "nonimmediate_operand" "xm")]))]
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"TARGET_SSE && !TARGET_SSE5"
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"cmp%D1ss\t{%3, %0|%0, %3}"
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(define_insn "*sse_setcc<mode>"
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[(set (match_operand:MODEF 0 "register_operand" "=x")
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(match_operator:MODEF 1 "sse_comparison_operator"
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[(match_operand:MODEF 2 "register_operand" "0")
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(match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
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"SSE_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
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"cmp%D1s<ssemodefsuffix>\t{%3, %0|%0, %3}"
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[(set_attr "type" "ssecmp")
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(set_attr "mode" "SF")])
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(define_insn "*sse_setccdf"
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[(set (match_operand:DF 0 "register_operand" "=x")
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(match_operator:DF 1 "sse_comparison_operator"
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[(match_operand:DF 2 "register_operand" "0")
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(match_operand:DF 3 "nonimmediate_operand" "xm")]))]
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"TARGET_SSE2 && !TARGET_SSE5"
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"cmp%D1sd\t{%3, %0|%0, %3}"
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[(set_attr "type" "ssecmp")
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(set_attr "mode" "DF")])
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(set_attr "mode" "<MODE>")])
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(define_insn "*sse5_setcc<mode>"
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[(set (match_operand:MODEF 0 "register_operand" "=x")
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@ -19663,41 +19653,25 @@
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;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
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;; are undefined in this condition, we're certain this is correct.
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(define_insn "sminsf3"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(smin:SF (match_operand:SF 1 "nonimmediate_operand" "%0")
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(match_operand:SF 2 "nonimmediate_operand" "xm")))]
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"TARGET_SSE_MATH"
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"minss\t{%2, %0|%0, %2}"
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(define_insn "smin<mode>3"
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[(set (match_operand:MODEF 0 "register_operand" "=x")
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(smin:MODEF
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(match_operand:MODEF 1 "nonimmediate_operand" "%0")
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(match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
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"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
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"mins<ssemodefsuffix>\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "SF")])
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(set_attr "mode" "<MODE>")])
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(define_insn "smaxsf3"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(smax:SF (match_operand:SF 1 "nonimmediate_operand" "%0")
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(match_operand:SF 2 "nonimmediate_operand" "xm")))]
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"TARGET_SSE_MATH"
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"maxss\t{%2, %0|%0, %2}"
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(define_insn "smax<mode>3"
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[(set (match_operand:MODEF 0 "register_operand" "=x")
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(smax:MODEF
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(match_operand:MODEF 1 "nonimmediate_operand" "%0")
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(match_operand:MODEF 2 "nonimmediate_operand" "xm")))]
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"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
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"maxs<ssemodefsuffix>\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "SF")])
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(define_insn "smindf3"
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[(set (match_operand:DF 0 "register_operand" "=x")
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(smin:DF (match_operand:DF 1 "nonimmediate_operand" "%0")
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(match_operand:DF 2 "nonimmediate_operand" "xm")))]
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"TARGET_SSE2 && TARGET_SSE_MATH"
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"minsd\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "DF")])
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(define_insn "smaxdf3"
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[(set (match_operand:DF 0 "register_operand" "=x")
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(smax:DF (match_operand:DF 1 "nonimmediate_operand" "%0")
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(match_operand:DF 2 "nonimmediate_operand" "xm")))]
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"TARGET_SSE2 && TARGET_SSE_MATH"
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"maxsd\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "DF")])
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(set_attr "mode" "<MODE>")])
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;; These versions of the min/max patterns implement exactly the operations
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;; min = (op1 < op2 ? op1 : op2)
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@ -19705,45 +19679,27 @@
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;; Their operands are not commutative, and thus they may be used in the
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;; presence of -0.0 and NaN.
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(define_insn "*ieee_sminsf3"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(unspec:SF [(match_operand:SF 1 "register_operand" "0")
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(match_operand:SF 2 "nonimmediate_operand" "xm")]
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UNSPEC_IEEE_MIN))]
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"TARGET_SSE_MATH"
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"minss\t{%2, %0|%0, %2}"
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(define_insn "*ieee_smin<mode>3"
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[(set (match_operand:MODEF 0 "register_operand" "=x")
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(unspec:MODEF
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[(match_operand:MODEF 1 "register_operand" "0")
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(match_operand:MODEF 2 "nonimmediate_operand" "xm")]
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UNSPEC_IEEE_MIN))]
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"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
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"mins<ssemodefsuffix>\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "SF")])
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(set_attr "mode" "<MODE>")])
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(define_insn "*ieee_smaxsf3"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(unspec:SF [(match_operand:SF 1 "register_operand" "0")
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(match_operand:SF 2 "nonimmediate_operand" "xm")]
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UNSPEC_IEEE_MAX))]
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"TARGET_SSE_MATH"
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"maxss\t{%2, %0|%0, %2}"
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(define_insn "*ieee_smax<mode>3"
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[(set (match_operand:MODEF 0 "register_operand" "=x")
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(unspec:MODEF
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[(match_operand:MODEF 1 "register_operand" "0")
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(match_operand:MODEF 2 "nonimmediate_operand" "xm")]
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UNSPEC_IEEE_MAX))]
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"SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
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"maxs<ssemodefsuffix>\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "SF")])
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(define_insn "*ieee_smindf3"
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[(set (match_operand:DF 0 "register_operand" "=x")
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(unspec:DF [(match_operand:DF 1 "register_operand" "0")
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(match_operand:DF 2 "nonimmediate_operand" "xm")]
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UNSPEC_IEEE_MIN))]
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"TARGET_SSE2 && TARGET_SSE_MATH"
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"minsd\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "DF")])
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(define_insn "*ieee_smaxdf3"
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[(set (match_operand:DF 0 "register_operand" "=x")
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(unspec:DF [(match_operand:DF 1 "register_operand" "0")
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(match_operand:DF 2 "nonimmediate_operand" "xm")]
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UNSPEC_IEEE_MAX))]
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"TARGET_SSE2 && TARGET_SSE_MATH"
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"maxsd\t{%2, %0|%0, %2}"
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[(set_attr "type" "sseadd")
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(set_attr "mode" "DF")])
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(set_attr "mode" "<MODE>")])
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;; Make two stack loads independent:
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;; fld aa fld aa
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