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i386.md (QImode and HImode cmove splitters): Merge QImode and HImode splitters. 

* config/i386/i386.md (QImode and HImode cmove splitters): Merge
	QImode and HImode splitters.  Use ix86_comparison_operator.
	Explicitly match FLAGS_REG.
	(DFmode cmove splitter): Explicitly match FLAGS_REG.

From-SVN: r189478
This commit is contained in:
Uros Bizjak 2012-07-14 09:42:08 +02:00
parent 21fd0bd667
commit d672a7854f
2 changed files with 40 additions and 45 deletions
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14
gcc/ChangeLog
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@ -1,3 +1,10 @@
2012-07-14 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (QImode and HImode cmove splitters): Merge
QImode and HImode splitters. Use ix86_comparison_operator.
Explicitly match FLAGS_REG.
(DFmode cmove splitter): Explicitly match FLAGS_REG.
2012-07-13 Richard Sandiford <rdsandiford@googlemail.com>
Steven Bosscher <steven@gcc.gnu.org>
Bernd Schmidt <bernds@codesourcery.com>
@ -163,8 +170,10 @@
2012-06-29 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
* configure: Regenerate.
Backport from mainline.
2012-03-15 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2012-03-15 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
* config.gcc (target_type_format_char): New. Document it. Set it for
arm*-*-* .
* configure.ac (gnu_unique_option): Use target_type_format_char
@ -173,7 +182,8 @@
2012-06-29 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
Backport from mainline.
2012-05-30 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
2012-05-30 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
* config/arm/arm.c (arm_evpc_neon_vrev): Adjust off by one error.
2012-06-28 Georg-Johann Lay <avr@gjlay.de>

71
gcc/config/i386/i386.md
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@ -16405,25 +16405,34 @@
[(set_attr "type" "icmov")
(set_attr "mode" "<MODE>")])
(define_insn_and_split "*movqicc_noc"
(define_insn "*movqicc_noc"
[(set (match_operand:QI 0 "register_operand" "=r,r")
(if_then_else:QI (match_operator 1 "ix86_comparison_operator"
[(match_operand 4 "flags_reg_operand" "")
(const_int 0)])
[(reg FLAGS_REG) (const_int 0)])
(match_operand:QI 2 "register_operand" "r,0")
(match_operand:QI 3 "register_operand" "0,r")))]
"TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL"
"#"
"&& reload_completed"
[(set (match_dup 0)
(if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
(match_dup 2)
(match_dup 3)))]
"operands[0] = gen_lowpart (SImode, operands[0]);
operands[2] = gen_lowpart (SImode, operands[2]);
operands[3] = gen_lowpart (SImode, operands[3]);"
[(set_attr "type" "icmov")
(set_attr "mode" "SI")])
(set_attr "mode" "QI")])
(define_split
[(set (match_operand 0 "register_operand")
(if_then_else (match_operator 1 "ix86_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(match_operand 2 "register_operand")
(match_operand 3 "register_operand")))]
"TARGET_CMOVE && !TARGET_PARTIAL_REG_STALL
&& (GET_MODE (operands[0]) == QImode
|| GET_MODE (operands[0]) == HImode)
&& reload_completed"
[(set (match_dup 0)
(if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
{
operands[0] = gen_lowpart (SImode, operands[0]);
operands[2] = gen_lowpart (SImode, operands[2]);
operands[3] = gen_lowpart (SImode, operands[3]);
})
(define_expand "mov<mode>cc"
[(set (match_operand:X87MODEF 0 "register_operand" "")
@ -16481,23 +16490,18 @@
(set_attr "mode" "DF,DF,DI,DI")])
(define_split
[(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
[(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand")
(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
[(match_operand 4 "flags_reg_operand" "")
(const_int 0)])
(match_operand:DF 2 "nonimmediate_operand" "")
(match_operand:DF 3 "nonimmediate_operand" "")))]
[(reg FLAGS_REG) (const_int 0)])
(match_operand:DF 2 "nonimmediate_operand")
(match_operand:DF 3 "nonimmediate_operand")))]
"!TARGET_64BIT && reload_completed"
[(set (match_dup 2)
(if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
(match_dup 5)
(match_dup 6)))
(if_then_else:SI (match_dup 1) (match_dup 4) (match_dup 5)))
(set (match_dup 3)
(if_then_else:SI (match_op_dup 1 [(match_dup 4) (const_int 0)])
(match_dup 7)
(match_dup 8)))]
(if_then_else:SI (match_dup 1) (match_dup 6) (match_dup 7)))]
{
split_double_mode (DImode, &operands[2], 2, &operands[5], &operands[7]);
split_double_mode (DImode, &operands[2], 2, &operands[4], &operands[6]);
split_double_mode (DImode, &operands[0], 1, &operands[2], &operands[3]);
})
@ -16910,25 +16914,6 @@
operands[0] = gen_lowpart (SImode, operands[0]);
operands[1] = gen_lowpart (SImode, operands[1]);
})
(define_split
[(set (match_operand 0 "register_operand" "")
(if_then_else (match_operator 1 "ordered_comparison_operator"
[(reg FLAGS_REG) (const_int 0)])
(match_operand 2 "register_operand" "")
(match_operand 3 "register_operand" "")))]
"! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
&& (GET_MODE (operands[0]) == HImode
|| (GET_MODE (operands[0]) == QImode
&& (TARGET_PROMOTE_QImode
|| optimize_insn_for_size_p ())))"
[(set (match_dup 0)
(if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
{
operands[0] = gen_lowpart (SImode, operands[0]);
operands[2] = gen_lowpart (SImode, operands[2]);
operands[3] = gen_lowpart (SImode, operands[3]);
})
;; RTL Peephole optimizations, run before sched2. These primarily look to
;; transform a complex memory operation into two memory to register operations.