arm.md (arm_mulsi3, [...]): Make conditional on !arm_arch6.
2007-01-04 Paul Brook <paul@codesourcery.com> * config/arm/arm.md (arm_mulsi3, thumb_mulsi3, mulsi3_compare0, mulsi_compare0_scratch, mulsi3addsi, mulsi3addsi_compare0, mulsi3addsi_compare0_scratch, mulsidi3adddi, mulsidi3, umulsidi3, umulsidi3adddi, smulsi3_highpart, umulsi3_highpart): Make conditional on !arm_arch6. (arm_mulsi3_v6, thumb_mulsi3_v6, mulsi3_compare0_v6, mulsi_compare0_scratch_v6, mulsi3addsi_v6, mulsi3addsi_compare0_v6, mulsi3addsi_compare0_scratch_v6, mulsidi3adddi_v6, mulsidi3_v6, umulsidi3_v6, umulsidi3adddi_v6, smulsi3_highpart_v6, umulsi3_highpart_v6): New insns. From-SVN: r120453
This commit is contained in:
Paul Brook
Paul Brook
parent
6d413586e0
commit
d6c397b0ff
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@ -1,3 +1,16 @@
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2007-01-04 Paul Brook <paul@codesourcery.com>
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* config/arm/arm.md (arm_mulsi3, thumb_mulsi3, mulsi3_compare0,
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mulsi_compare0_scratch, mulsi3addsi, mulsi3addsi_compare0,
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mulsi3addsi_compare0_scratch, mulsidi3adddi, mulsidi3,
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umulsidi3, umulsidi3adddi, smulsi3_highpart,
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umulsi3_highpart): Make conditional on !arm_arch6.
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(arm_mulsi3_v6, thumb_mulsi3_v6, mulsi3_compare0_v6,
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mulsi_compare0_scratch_v6, mulsi3addsi_v6, mulsi3addsi_compare0_v6,
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mulsi3addsi_compare0_scratch_v6, mulsidi3adddi_v6, mulsidi3_v6,
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umulsidi3_v6, umulsidi3adddi_v6, smulsi3_highpart_v6,
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umulsi3_highpart_v6): New insns.
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2007-01-04 Roger Sayle <roger@eyesopen.com>
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* fold-const.c (fold_convert): When casting an expression to void,
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@ -1101,12 +1101,22 @@
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[(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
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(mult:SI (match_operand:SI 2 "s_register_operand" "r,r")
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(match_operand:SI 1 "s_register_operand" "%?r,0")))]
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"TARGET_32BIT"
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"TARGET_32BIT && !arm_arch6"
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"mul%?\\t%0, %2, %1"
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[(set_attr "insn" "mul")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*arm_mulsi3_v6"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(mult:SI (match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "s_register_operand" "r")))]
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"TARGET_32BIT && arm_arch6"
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"mul%?\\t%0, %1, %2"
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[(set_attr "insn" "mul")
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(set_attr "predicable" "yes")]
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)
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; Unfortunately with the Thumb the '&'/'0' trick can fails when operands
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; 1 and 2; are the same, because reload will make operand 0 match
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; operand 1 without realizing that this conflicts with operand 2. We fix
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@ -1116,7 +1126,7 @@
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[(set (match_operand:SI 0 "register_operand" "=&l,&l,&l")
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(mult:SI (match_operand:SI 1 "register_operand" "%l,*h,0")
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(match_operand:SI 2 "register_operand" "l,l,l")))]
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"TARGET_THUMB1"
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"TARGET_THUMB1 && !arm_arch6"
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"*
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if (which_alternative < 2)
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return \"mov\\t%0, %1\;mul\\t%0, %2\";
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@ -1127,6 +1137,19 @@
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(set_attr "insn" "mul")]
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)
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(define_insn "*thumb_mulsi3_v6"
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[(set (match_operand:SI 0 "register_operand" "=l,l,l")
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(mult:SI (match_operand:SI 1 "register_operand" "0,l,0")
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(match_operand:SI 2 "register_operand" "l,0,0")))]
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"TARGET_THUMB1 && arm_arch6"
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"@
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mul\\t%0, %2
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mul\\t%0, %1
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mul\\t%0, %1"
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[(set_attr "length" "2")
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(set_attr "insn" "mul")]
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)
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(define_insn "*mulsi3_compare0"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV (mult:SI
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@ -1135,7 +1158,21 @@
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(const_int 0)))
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(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
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(mult:SI (match_dup 2) (match_dup 1)))]
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"TARGET_ARM"
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"TARGET_ARM && !arm_arch6"
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"mul%.\\t%0, %2, %1"
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[(set_attr "conds" "set")
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(set_attr "insn" "muls")]
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)
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(define_insn "*mulsi3_compare0_v6"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV (mult:SI
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(match_operand:SI 2 "s_register_operand" "r")
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(match_operand:SI 1 "s_register_operand" "r"))
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(const_int 0)))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(mult:SI (match_dup 2) (match_dup 1)))]
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"TARGET_ARM && arm_arch6 && optimize_size"
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"mul%.\\t%0, %2, %1"
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[(set_attr "conds" "set")
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(set_attr "insn" "muls")]
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@ -1148,7 +1185,20 @@
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(match_operand:SI 1 "s_register_operand" "%?r,0"))
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(const_int 0)))
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(clobber (match_scratch:SI 0 "=&r,&r"))]
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"TARGET_ARM"
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"TARGET_ARM && !arm_arch6"
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"mul%.\\t%0, %2, %1"
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[(set_attr "conds" "set")
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(set_attr "insn" "muls")]
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)
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(define_insn "*mulsi_compare0_scratch_v6"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV (mult:SI
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(match_operand:SI 2 "s_register_operand" "r")
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(match_operand:SI 1 "s_register_operand" "r"))
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(const_int 0)))
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(clobber (match_scratch:SI 0 "=r"))]
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"TARGET_ARM && arm_arch6 && optimize_size"
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"mul%.\\t%0, %2, %1"
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[(set_attr "conds" "set")
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(set_attr "insn" "muls")]
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@ -1162,7 +1212,19 @@
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(mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r")
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(match_operand:SI 1 "s_register_operand" "%r,0,r,0"))
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(match_operand:SI 3 "s_register_operand" "?r,r,0,0")))]
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"TARGET_32BIT"
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"TARGET_32BIT && !arm_arch6"
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"mla%?\\t%0, %2, %1, %3"
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[(set_attr "insn" "mla")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*mulsi3addsi_v6"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI
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(mult:SI (match_operand:SI 2 "s_register_operand" "r")
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(match_operand:SI 1 "s_register_operand" "r"))
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(match_operand:SI 3 "s_register_operand" "r")))]
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"TARGET_32BIT && arm_arch6"
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"mla%?\\t%0, %2, %1, %3"
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[(set_attr "insn" "mla")
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(set_attr "predicable" "yes")]
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@ -1179,7 +1241,24 @@
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(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r")
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(plus:SI (mult:SI (match_dup 2) (match_dup 1))
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(match_dup 3)))]
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"TARGET_ARM"
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"TARGET_ARM && arm_arch6"
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"mla%.\\t%0, %2, %1, %3"
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[(set_attr "conds" "set")
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(set_attr "insn" "mlas")]
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)
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(define_insn "*mulsi3addsi_compare0_v6"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV
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(plus:SI (mult:SI
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(match_operand:SI 2 "s_register_operand" "r")
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(match_operand:SI 1 "s_register_operand" "r"))
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(match_operand:SI 3 "s_register_operand" "r"))
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(const_int 0)))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (mult:SI (match_dup 2) (match_dup 1))
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(match_dup 3)))]
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"TARGET_ARM && arm_arch6 && optimize_size"
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"mla%.\\t%0, %2, %1, %3"
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[(set_attr "conds" "set")
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(set_attr "insn" "mlas")]
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@ -1194,7 +1273,22 @@
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(match_operand:SI 3 "s_register_operand" "?r,r,0,0"))
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(const_int 0)))
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(clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))]
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"TARGET_ARM"
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"TARGET_ARM && !arm_arch6"
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"mla%.\\t%0, %2, %1, %3"
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[(set_attr "conds" "set")
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(set_attr "insn" "mlas")]
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)
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(define_insn "*mulsi3addsi_compare0_scratch_v6"
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[(set (reg:CC_NOOV CC_REGNUM)
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(compare:CC_NOOV
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(plus:SI (mult:SI
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(match_operand:SI 2 "s_register_operand" "r")
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(match_operand:SI 1 "s_register_operand" "r"))
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(match_operand:SI 3 "s_register_operand" "r"))
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(const_int 0)))
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(clobber (match_scratch:SI 0 "=r"))]
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"TARGET_ARM && arm_arch6 && optimize_size"
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"mla%.\\t%0, %2, %1, %3"
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[(set_attr "conds" "set")
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(set_attr "insn" "mlas")]
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@ -1209,7 +1303,20 @@
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(sign_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
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(sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
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(match_operand:DI 1 "s_register_operand" "0")))]
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"TARGET_32BIT && arm_arch3m"
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"TARGET_32BIT && arm_arch3m && !arm_arch6"
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"smlal%?\\t%Q0, %R0, %3, %2"
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[(set_attr "insn" "smlal")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*mulsidi3adddi_v6"
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[(set (match_operand:DI 0 "s_register_operand" "=r")
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(plus:DI
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(mult:DI
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(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))
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(sign_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
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(match_operand:DI 1 "s_register_operand" "0")))]
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"TARGET_32BIT && arm_arch6"
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"smlal%?\\t%Q0, %R0, %3, %2"
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[(set_attr "insn" "smlal")
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(set_attr "predicable" "yes")]
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@ -1220,7 +1327,18 @@
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(mult:DI
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(sign_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
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(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
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"TARGET_32BIT && arm_arch3m"
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"TARGET_32BIT && arm_arch3m && !arm_arch6"
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"smull%?\\t%Q0, %R0, %1, %2"
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[(set_attr "insn" "smull")
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(set_attr "predicable" "yes")]
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)
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(define_insn "mulsidi3_v6"
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[(set (match_operand:DI 0 "s_register_operand" "=r")
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(mult:DI
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(sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
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(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
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"TARGET_32BIT && arm_arch6"
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"smull%?\\t%Q0, %R0, %1, %2"
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[(set_attr "insn" "smull")
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(set_attr "predicable" "yes")]
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@ -1231,7 +1349,18 @@
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(mult:DI
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(zero_extend:DI (match_operand:SI 1 "s_register_operand" "%r"))
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(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
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"TARGET_32BIT && arm_arch3m"
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"TARGET_32BIT && arm_arch3m && !arm_arch6"
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"umull%?\\t%Q0, %R0, %1, %2"
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[(set_attr "insn" "umull")
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(set_attr "predicable" "yes")]
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)
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(define_insn "umulsidi3_v6"
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[(set (match_operand:DI 0 "s_register_operand" "=r")
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(mult:DI
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(zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
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(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))]
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"TARGET_32BIT && arm_arch6"
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"umull%?\\t%Q0, %R0, %1, %2"
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[(set_attr "insn" "umull")
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(set_attr "predicable" "yes")]
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@ -1246,7 +1375,20 @@
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(zero_extend:DI (match_operand:SI 2 "s_register_operand" "%r"))
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(zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
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(match_operand:DI 1 "s_register_operand" "0")))]
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"TARGET_32BIT && arm_arch3m"
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"TARGET_32BIT && arm_arch3m && !arm_arch6"
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"umlal%?\\t%Q0, %R0, %3, %2"
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[(set_attr "insn" "umlal")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*umulsidi3adddi_v6"
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[(set (match_operand:DI 0 "s_register_operand" "=r")
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(plus:DI
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(mult:DI
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(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))
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(zero_extend:DI (match_operand:SI 3 "s_register_operand" "r")))
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(match_operand:DI 1 "s_register_operand" "0")))]
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"TARGET_32BIT && arm_arch6"
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"umlal%?\\t%Q0, %R0, %3, %2"
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[(set_attr "insn" "umlal")
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(set_attr "predicable" "yes")]
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@ -1261,7 +1403,22 @@
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(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 "=&r,&r"))]
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"TARGET_32BIT && arm_arch3m"
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"TARGET_32BIT && arm_arch3m && !arm_arch6"
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"smull%?\\t%3, %0, %2, %1"
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[(set_attr "insn" "smull")
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(set_attr "predicable" "yes")]
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)
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(define_insn "smulsi3_highpart_v6"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(truncate:SI
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(lshiftrt:DI
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(mult:DI
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(sign_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
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(sign_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 "=r"))]
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"TARGET_32BIT && arm_arch6"
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"smull%?\\t%3, %0, %2, %1"
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[(set_attr "insn" "smull")
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(set_attr "predicable" "yes")]
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@ -1276,7 +1433,22 @@
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(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 "=&r,&r"))]
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"TARGET_32BIT && arm_arch3m"
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"TARGET_32BIT && arm_arch3m && !arm_arch6"
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"umull%?\\t%3, %0, %2, %1"
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[(set_attr "insn" "umull")
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(set_attr "predicable" "yes")]
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)
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(define_insn "umulsi3_highpart_v6"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(truncate:SI
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(lshiftrt:DI
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(mult:DI
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(zero_extend:DI (match_operand:SI 1 "s_register_operand" "r"))
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(zero_extend:DI (match_operand:SI 2 "s_register_operand" "r")))
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(const_int 32))))
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(clobber (match_scratch:SI 3 "=r"))]
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"TARGET_32BIT && arm_arch6"
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"umull%?\\t%3, %0, %2, %1"
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[(set_attr "insn" "umull")
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(set_attr "predicable" "yes")]
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