re PR tree-optimization/89386 (Generation of vectorized MULHRS (Multiply High with Round and Scale) instruction)
PR tree-optimization/89386 * config/i386/sse.md (smulhrs<mode>3): New expander. (smulhrsv4hi3): Ditto. testsuite/ChangeLog: PR tree-optimization/89386 * gcc.target/i386/pr89386.c: New test. * gcc.target/i386/pr89386-1.c: Ditto. From-SVN: r275689
This commit is contained in:
Uros Bizjak
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bdc91a3299
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d6ecb707cc
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@ -1,3 +1,9 @@
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2019-09-12 Uroš Bizjak <ubizjak@gmail.com>
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PR tree-optimization/89386
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* config/i386/sse.md (smulhrs<mode>3): New expander.
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(smulhrsv4hi3): Ditto.
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2019-09-12 Richard Biener <rguenther@suse.de>
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PR tree-optimization/91750
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@ -27,15 +33,6 @@
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* tree-vect-patterns.c (vect_recog_mulhs_pattern): New pattern
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function.
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(vect_vect_recog_func_ptrs): Add it.
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* testsuite/gcc.target/aarch64/sve2/mulhrs_1.c: New test.
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* testsuite/gcc.dg/vect/vect-mulhrs-1.c: As above.
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* testsuite/gcc.dg/vect/vect-mulhrs-2.c: As above.
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* testsuite/gcc.dg/vect/vect-mulhrs-3.c: As above.
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* testsuite/gcc.dg/vect/vect-mulhrs-4.c: As above.
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* doc/sourcebuild.texi (vect_mulhrs_hi): Document new target selector.
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* testsuite/lib/target-supports.exp
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(check_effective_target_vect_mulhrs_hi): Return true for AArch64
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with SVE2.
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2019-09-11 Michael Meissner <meissner@linux.ibm.com>
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@ -16475,6 +16475,26 @@
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ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);
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})
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(define_expand "smulhrs<mode>3"
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[(set (match_operand:VI2_AVX2 0 "register_operand")
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(truncate:VI2_AVX2
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(lshiftrt:<ssedoublemode>
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(plus:<ssedoublemode>
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(lshiftrt:<ssedoublemode>
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(mult:<ssedoublemode>
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(sign_extend:<ssedoublemode>
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(match_operand:VI2_AVX2 1 "nonimmediate_operand"))
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(sign_extend:<ssedoublemode>
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(match_operand:VI2_AVX2 2 "nonimmediate_operand")))
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(const_int 14))
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(match_dup 3))
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(const_int 1))))]
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"TARGET_SSSE3"
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{
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operands[3] = CONST1_RTX(<MODE>mode);
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ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);
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})
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(define_insn "*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>"
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[(set (match_operand:VI2_AVX2 0 "register_operand" "=x,x,v")
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(truncate:VI2_AVX2
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@ -16502,6 +16522,26 @@
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(set_attr "prefix" "orig,maybe_evex,evex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_expand "smulhrsv4hi3"
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[(set (match_operand:V4HI 0 "register_operand")
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(truncate:V4HI
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(lshiftrt:V4SI
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(plus:V4SI
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(lshiftrt:V4SI
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(mult:V4SI
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(sign_extend:V4SI
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(match_operand:V4HI 1 "register_operand"))
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(sign_extend:V4SI
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(match_operand:V4HI 2 "register_operand")))
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(const_int 14))
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(match_dup 3))
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(const_int 1))))]
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"TARGET_MMX_WITH_SSE && TARGET_SSSE3"
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{
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operands[3] = CONST1_RTX(V4HImode);
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ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);
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})
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(define_expand "ssse3_pmulhrswv4hi3"
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[(set (match_operand:V4HI 0 "register_operand")
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(truncate:V4HI
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@ -1,8 +1,27 @@
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2019-09-12 Uroš Bizjak <ubizjak@gmail.com>
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PR tree-optimization/89386
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* gcc.target/i386/pr89386.c: New test.
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* gcc.target/i386/pr89386-1.c: Ditto.
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2019-09-12 Richard Biener <rguenther@suse.de>
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PR tree-optimization/91750
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* gcc.dg/vect/pr91750.c: New testcase.
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2019-09-12 Yuliang Wang <yuliang.wang@arm.com>
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PR tree-optimization/89386
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* testsuite/gcc.target/aarch64/sve2/mulhrs_1.c: New test.
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* testsuite/gcc.dg/vect/vect-mulhrs-1.c: As above.
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* testsuite/gcc.dg/vect/vect-mulhrs-2.c: As above.
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* testsuite/gcc.dg/vect/vect-mulhrs-3.c: As above.
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* testsuite/gcc.dg/vect/vect-mulhrs-4.c: As above.
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* doc/sourcebuild.texi (vect_mulhrs_hi): Document new target selector.
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* testsuite/lib/target-supports.exp
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(check_effective_target_vect_mulhrs_hi): Return true for AArch64
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with SVE2.
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2019-09-11 Sandra Loosemore <sandra@codesourcery.com>
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PR testsuite/83889
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@ -0,0 +1,16 @@
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/* { dg-do compile { target { ! ia32 } } } */
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/* { dg-options "-mssse3 -O2 -ftree-vectorize" } */
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#define N 4
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short a[N], b[N], c[N];
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int foo (void)
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{
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int i;
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for (i = 0; i < N; i++)
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a[i] = ((((int) b[i] * (int) c[i]) >> 14) + 1) >> 1;
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}
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/* { dg-final { scan-assembler "pmulhrsw" } } */
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@ -0,0 +1,16 @@
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/* { dg-do compile } */
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/* { dg-options "-mssse3 -O2 -ftree-vectorize" } */
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#define N 1024
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short a[N], b[N], c[N];
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int foo (void)
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{
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int i;
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for (i = 0; i < N; i++)
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a[i] = ((((int) b[i] * (int) c[i]) >> 14) + 1) >> 1;
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}
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/* { dg-final { scan-assembler "pmulhrsw" } } */
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