arm.c (arm_issue_rate): Return 2 for Cortex-A5.
* config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5. * config/arm/arm.md (generic_sched): No for Cortex-A5. (generic_vfp): Likewise. (cortex-a5.md): Include. * config/arm/cortex-a5.md: New. From-SVN: r163550
This commit is contained in:
Julian Brown
Mark Mitchell
parent
0ceb020134
commit
d8099dd859
@ -1,3 +1,11 @@
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2010-08-25 Julian Brown <julian@codesourcery.com>
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* config/arm/arm.c (arm_issue_rate): Return 2 for Cortex-A5.
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* config/arm/arm.md (generic_sched): No for Cortex-A5.
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(generic_vfp): Likewise.
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(cortex-a5.md): Include.
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* config/arm/cortex-a5.md: New.
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2010-08-25 Richard Guenther <rguenther@suse.de>
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* alias.c (get_alias_set): Assign a single alias-set to
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@ -22446,6 +22446,7 @@ arm_issue_rate (void)
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{
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case cortexr4:
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case cortexr4f:
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case cortexa5:
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case cortexa8:
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case cortexa9:
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return 2;
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@ -495,7 +495,7 @@
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(define_attr "generic_sched" "yes,no"
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(const (if_then_else
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(ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9")
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(ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa5,cortexa8,cortexa9")
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(eq_attr "tune_cortexr4" "yes"))
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(const_string "no")
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(const_string "yes"))))
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@ -503,7 +503,7 @@
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(define_attr "generic_vfp" "yes,no"
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(const (if_then_else
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(and (eq_attr "fpu" "vfp")
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(eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9")
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(eq_attr "tune" "!arm1020e,arm1022e,cortexa5,cortexa8,cortexa9")
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(eq_attr "tune_cortexr4" "no"))
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(const_string "yes")
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(const_string "no"))))
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@ -513,6 +513,7 @@
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(include "arm1020e.md")
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(include "arm1026ejs.md")
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(include "arm1136jfs.md")
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(include "cortex-a5.md")
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(include "cortex-a8.md")
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(include "cortex-a9.md")
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(include "cortex-r4.md")
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297
gcc/config/arm/cortex-a5.md
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297
gcc/config/arm/cortex-a5.md
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@ -0,0 +1,297 @@
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;; ARM Cortex-A5 pipeline description
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;; Copyright (C) 2010 Free Software Foundation, Inc.
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;; Contributed by CodeSourcery.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify it
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;; under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 3, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful, but
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;; WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;; General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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(define_automaton "cortex_a5")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Functional units.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; The integer (ALU) pipeline. There are five DPU pipeline
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;; stages. However the decode/issue stages operate the same for all
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;; instructions, so do not model them. We only need to model the
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;; first execute stage because instructions always advance one stage
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;; per cycle in order. Only branch instructions may dual-issue, so a
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;; single unit covers all of the LS, ALU, MAC and FPU pipelines.
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(define_cpu_unit "cortex_a5_ex1" "cortex_a5")
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;; The branch pipeline. Branches can dual-issue with other instructions
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;; (except when those instructions take multiple cycles to issue).
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(define_cpu_unit "cortex_a5_branch" "cortex_a5")
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;; Pseudo-unit for blocking the multiply pipeline when a double-precision
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;; multiply is in progress.
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(define_cpu_unit "cortex_a5_fpmul_pipe" "cortex_a5")
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;; The floating-point add pipeline (ex1/f1 stage), used to model the usage
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;; of the add pipeline by fmac instructions, etc.
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(define_cpu_unit "cortex_a5_fpadd_pipe" "cortex_a5")
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;; Floating-point div/sqrt (long latency, out-of-order completion).
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(define_cpu_unit "cortex_a5_fp_div_sqrt" "cortex_a5")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ALU instructions.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_insn_reservation "cortex_a5_alu" 2
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "alu"))
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"cortex_a5_ex1")
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(define_insn_reservation "cortex_a5_alu_shift" 2
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "alu_shift,alu_shift_reg"))
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"cortex_a5_ex1")
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;; Forwarding path for unshifted operands.
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(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
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"cortex_a5_alu")
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(define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
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"cortex_a5_alu_shift"
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"arm_no_early_alu_shift_dep")
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;; The multiplier pipeline can forward results from wr stage only so
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;; there's no need to specify bypasses).
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(define_insn_reservation "cortex_a5_mul" 2
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "mult"))
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"cortex_a5_ex1")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Load/store instructions.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Address-generation happens in the issue stage, which is one stage behind
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;; the ex1 stage (the first stage we care about for scheduling purposes). The
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;; dc1 stage is parallel with ex1, dc2 with ex2 and rot with wr.
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(define_insn_reservation "cortex_a5_load1" 2
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "load_byte,load1"))
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"cortex_a5_ex1")
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(define_insn_reservation "cortex_a5_store1" 0
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "store1"))
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"cortex_a5_ex1")
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(define_insn_reservation "cortex_a5_load2" 3
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "load2"))
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"cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
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(define_insn_reservation "cortex_a5_store2" 0
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "store2"))
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"cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
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(define_insn_reservation "cortex_a5_load3" 4
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "load3"))
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"cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
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cortex_a5_ex1")
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(define_insn_reservation "cortex_a5_store3" 0
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "store3"))
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"cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
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cortex_a5_ex1")
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(define_insn_reservation "cortex_a5_load4" 5
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "load3"))
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"cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
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cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
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(define_insn_reservation "cortex_a5_store4" 0
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "store3"))
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"cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1+cortex_a5_branch,\
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cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Branches.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Direct branches are the only instructions we can dual-issue (also IT and
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;; nop, but those aren't very interesting for scheduling). (The latency here
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;; is meant to represent when the branch actually takes place, but may not be
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;; entirely correct.)
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(define_insn_reservation "cortex_a5_branch" 3
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "branch,call"))
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"cortex_a5_branch")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Floating-point arithmetic.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_insn_reservation "cortex_a5_fpalu" 4
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fcpys, fmuls, f_cvt,\
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fcmps, fcmpd"))
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"cortex_a5_ex1+cortex_a5_fpadd_pipe")
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;; For fconsts and fconstd, 8-bit immediate data is passed directly from
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;; f1 to f3 (which I think reduces the latency by one cycle).
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(define_insn_reservation "cortex_a5_fconst" 3
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "fconsts,fconstd"))
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"cortex_a5_ex1+cortex_a5_fpadd_pipe")
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;; We should try not to attempt to issue a single-precision multiplication in
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;; the middle of a double-precision multiplication operation (the usage of
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;; cortex_a5_fpmul_pipe).
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(define_insn_reservation "cortex_a5_fpmuls" 4
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "fmuls"))
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"cortex_a5_ex1+cortex_a5_fpmul_pipe")
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;; For single-precision multiply-accumulate, the add (accumulate) is issued
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;; whilst the multiply is in F4. The multiply result can then be forwarded
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;; from F5 to F1. The issue unit is only used once (when we first start
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;; processing the instruction), but the usage of the FP add pipeline could
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;; block other instructions attempting to use it simultaneously. We try to
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;; avoid that using cortex_a5_fpadd_pipe.
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(define_insn_reservation "cortex_a5_fpmacs" 8
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "fmacs"))
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"cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
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;; Non-multiply instructions can issue in the middle two instructions of a
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;; double-precision multiply. Note that it isn't entirely clear when a branch
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;; can dual-issue when a multi-cycle multiplication is in progress; we ignore
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;; that for now though.
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(define_insn_reservation "cortex_a5_fpmuld" 7
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "fmuld"))
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"cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
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cortex_a5_ex1+cortex_a5_fpmul_pipe")
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(define_insn_reservation "cortex_a5_fpmacd" 11
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "fmacd"))
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"cortex_a5_ex1+cortex_a5_fpmul_pipe, cortex_a5_fpmul_pipe*2,\
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cortex_a5_ex1+cortex_a5_fpmul_pipe, nothing*3, cortex_a5_fpadd_pipe")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; Floating-point divide/square root instructions.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ??? Not sure if the 14 cycles taken for single-precision divide to complete
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;; includes the time taken for the special instruction used to collect the
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;; result to travel down the multiply pipeline, or not. Assuming so. (If
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;; that's wrong, the latency should be increased by a few cycles.)
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;; fsqrt takes one cycle less, but that is not modelled, nor is the use of the
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;; multiply pipeline to collect the divide/square-root result.
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(define_insn_reservation "cortex_a5_fdivs" 14
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "fdivs"))
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"cortex_a5_ex1, cortex_a5_fp_div_sqrt * 13")
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;; ??? Similarly for fdivd.
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(define_insn_reservation "cortex_a5_fdivd" 29
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "fdivd"))
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"cortex_a5_ex1, cortex_a5_fp_div_sqrt * 28")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; VFP to/from core transfers.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; FP loads take data from wr/rot/f3.
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;; Core-to-VFP transfers use the multiply pipeline.
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(define_insn_reservation "cortex_a5_r2f" 4
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "r_2_f"))
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"cortex_a5_ex1")
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(define_insn_reservation "cortex_a5_f2r" 2
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "f_2_r"))
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"cortex_a5_ex1")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; VFP flag transfer.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; ??? The flag forwarding from fmstat to the ex2 stage of the second
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;; instruction is not modeled at present.
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(define_insn_reservation "cortex_a5_f_flags" 4
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "f_flag"))
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"cortex_a5_ex1")
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; VFP load/store.
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||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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(define_insn_reservation "cortex_a5_f_loads" 4
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "f_loads"))
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"cortex_a5_ex1")
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(define_insn_reservation "cortex_a5_f_loadd" 5
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "f_load,f_loadd"))
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"cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
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||||
(define_insn_reservation "cortex_a5_f_stores" 0
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(and (eq_attr "tune" "cortexa5")
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(eq_attr "type" "f_stores"))
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"cortex_a5_ex1")
|
||||
|
||||
(define_insn_reservation "cortex_a5_f_stored" 0
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||||
(and (eq_attr "tune" "cortexa5")
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||||
(eq_attr "type" "f_store,f_stored"))
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"cortex_a5_ex1+cortex_a5_branch, cortex_a5_ex1")
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||||
;; Load-to-use for floating-point values has a penalty of one cycle,
|
||||
;; i.e. a latency of two.
|
||||
|
||||
(define_bypass 2 "cortex_a5_f_loads"
|
||||
"cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
|
||||
cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
|
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cortex_a5_f2r")
|
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||||
(define_bypass 3 "cortex_a5_f_loadd"
|
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"cortex_a5_fpalu, cortex_a5_fpmacs, cortex_a5_fpmuld,\
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cortex_a5_fpmacd, cortex_a5_fdivs, cortex_a5_fdivd,\
|
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cortex_a5_f2r")
|
||||
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Block a user