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Enable bt and and movzx for Lakemont 

* config/i386/x86-tune.def (X86_TUNE_USE_BT): Enable for
	Lakemont.
	(X86_TUNE_ZERO_EXTEND_WITH_AND): Disable for Lakemont.

From-SVN: r228337
This commit is contained in:
H.J. Lu 2015-10-01 13:34:49 +00:00 committed by H.J. Lu
parent 91470073d6
commit d878e79bf8
2 changed files with 8 additions and 2 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2015-10-01 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/x86-tune.def (X86_TUNE_USE_BT): Enable for
Lakemont.
(X86_TUNE_ZERO_EXTEND_WITH_AND): Disable for Lakemont.
2015-10-01 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/aarch-common-protos.h

4
gcc/config/i386/x86-tune.def
View File

@ -292,7 +292,7 @@ DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
/* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_INTEL
| m_AMD_MULTIPLE | m_GENERIC)
| m_LAKEMONT | m_AMD_MULTIPLE | m_GENERIC)
/*****************************************************************************/
/* 387 instruction selection tuning */
@ -448,7 +448,7 @@ DEF_TUNE (X86_TUNE_SHIFT1, "shift1", ~m_486)
/* X86_TUNE_ZERO_EXTEND_WITH_AND: Use AND instruction instead
of mozbl/movwl. */
DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND, "zero_extend_with_and",
m_486 | m_PENT | m_LAKEMONT)
m_486 | m_PENT)
/* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
and SImode multiply, but 386 and 486 do HImode multiply faster. */