From d9128d88e65d57fc0b54efd76dd63841d054a3bb Mon Sep 17 00:00:00 2001 From: Andreas Krebbel Date: Fri, 19 Feb 2016 10:39:15 +0000 Subject: [PATCH] S/390: z13 Add missing commutative operand markers. gcc/ChangeLog: * config/s390/vector.md: Add missing commutative operand markers to the patterns which qualify for one. * config/s390/vx-builtins.md: Likewise. From-SVN: r233556 --- gcc/ChangeLog | 6 +++++ gcc/config/s390/vector.md | 44 +++++++++++++++++----------------- gcc/config/s390/vx-builtins.md | 44 +++++++++++++++++----------------- 3 files changed, 50 insertions(+), 44 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d932ee884bb..083e8287817 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-02-19 Andreas Krebbel + + * config/s390/vector.md: Add missing commutative operand markers + to the patterns which qualify for one. + * config/s390/vx-builtins.md: Likewise. + 2016-02-19 Andreas Krebbel * config/s390/vector.md (VI, VI_QHS): Add single element vector diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 3101057506f..cc3287c78ff 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -453,8 +453,8 @@ ; operation into two DImode ADDs. (define_insn "add3" [(set (match_operand:VIT 0 "nonimmediate_operand" "=v") - (plus:VIT (match_operand:VIT 1 "nonimmediate_operand" "v") - (match_operand:VIT 2 "general_operand" "v")))] + (plus:VIT (match_operand:VIT 1 "nonimmediate_operand" "%v") + (match_operand:VIT 2 "general_operand" "v")))] "TARGET_VX" "va\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) @@ -471,7 +471,7 @@ ; vmlb, vmlhw, vmlf (define_insn "mul3" [(set (match_operand:VI_QHS 0 "register_operand" "=v") - (mult:VI_QHS (match_operand:VI_QHS 1 "register_operand" "v") + (mult:VI_QHS (match_operand:VI_QHS 1 "register_operand" "%v") (match_operand:VI_QHS 2 "register_operand" "v")))] "TARGET_VX" "vml\t%v0,%v1,%v2" @@ -526,7 +526,7 @@ (define_insn "and3" [(set (match_operand:VT 0 "register_operand" "=v") - (and:VT (match_operand:VT 1 "register_operand" "v") + (and:VT (match_operand:VT 1 "register_operand" "%v") (match_operand:VT 2 "register_operand" "v")))] "TARGET_VX" "vn\t%v0,%v1,%v2" @@ -537,7 +537,7 @@ (define_insn "ior3" [(set (match_operand:VT 0 "register_operand" "=v") - (ior:VT (match_operand:VT 1 "register_operand" "v") + (ior:VT (match_operand:VT 1 "register_operand" "%v") (match_operand:VT 2 "register_operand" "v")))] "TARGET_VX" "vo\t%v0,%v1,%v2" @@ -548,7 +548,7 @@ (define_insn "xor3" [(set (match_operand:VT 0 "register_operand" "=v") - (xor:VT (match_operand:VT 1 "register_operand" "v") + (xor:VT (match_operand:VT 1 "register_operand" "%v") (match_operand:VT 2 "register_operand" "v")))] "TARGET_VX" "vx\t%v0,%v1,%v2" @@ -765,7 +765,7 @@ ; vmnb, vmnh, vmnf, vmng (define_insn "smin3" [(set (match_operand:VI 0 "register_operand" "=v") - (smin:VI (match_operand:VI 1 "register_operand" "v") + (smin:VI (match_operand:VI 1 "register_operand" "%v") (match_operand:VI 2 "register_operand" "v")))] "TARGET_VX" "vmn\t%v0,%v1,%v2" @@ -774,7 +774,7 @@ ; vmxb, vmxh, vmxf, vmxg (define_insn "smax3" [(set (match_operand:VI 0 "register_operand" "=v") - (smax:VI (match_operand:VI 1 "register_operand" "v") + (smax:VI (match_operand:VI 1 "register_operand" "%v") (match_operand:VI 2 "register_operand" "v")))] "TARGET_VX" "vmx\t%v0,%v1,%v2" @@ -783,7 +783,7 @@ ; vmnlb, vmnlh, vmnlf, vmnlg (define_insn "umin3" [(set (match_operand:VI 0 "register_operand" "=v") - (umin:VI (match_operand:VI 1 "register_operand" "v") + (umin:VI (match_operand:VI 1 "register_operand" "%v") (match_operand:VI 2 "register_operand" "v")))] "TARGET_VX" "vmnl\t%v0,%v1,%v2" @@ -792,7 +792,7 @@ ; vmxlb, vmxlh, vmxlf, vmxlg (define_insn "umax3" [(set (match_operand:VI 0 "register_operand" "=v") - (umax:VI (match_operand:VI 1 "register_operand" "v") + (umax:VI (match_operand:VI 1 "register_operand" "%v") (match_operand:VI 2 "register_operand" "v")))] "TARGET_VX" "vmxl\t%v0,%v1,%v2" @@ -800,8 +800,8 @@ ; vmeb, vmeh, vmef (define_insn "vec_widen_smult_even_" - [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_QHS 1 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") (match_operand:VI_QHS 2 "register_operand" "v")] UNSPEC_VEC_SMULT_EVEN))] "TARGET_VX" @@ -811,7 +811,7 @@ ; vmleb, vmleh, vmlef (define_insn "vec_widen_umult_even_" [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_QHS 1 "register_operand" "v") + (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") (match_operand:VI_QHS 2 "register_operand" "v")] UNSPEC_VEC_UMULT_EVEN))] "TARGET_VX" @@ -821,7 +821,7 @@ ; vmob, vmoh, vmof (define_insn "vec_widen_smult_odd_" [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_QHS 1 "register_operand" "v") + (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") (match_operand:VI_QHS 2 "register_operand" "v")] UNSPEC_VEC_SMULT_ODD))] "TARGET_VX" @@ -831,7 +831,7 @@ ; vmlob, vmloh, vmlof (define_insn "vec_widen_umult_odd_" [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_QHS 1 "register_operand" "v") + (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") (match_operand:VI_QHS 2 "register_operand" "v")] UNSPEC_VEC_UMULT_ODD))] "TARGET_VX" @@ -854,7 +854,7 @@ (define_insn "addv2df3" [(set (match_operand:V2DF 0 "register_operand" "=v") - (plus:V2DF (match_operand:V2DF 1 "register_operand" "v") + (plus:V2DF (match_operand:V2DF 1 "register_operand" "%v") (match_operand:V2DF 2 "register_operand" "v")))] "TARGET_VX" "vfadb\t%v0,%v1,%v2" @@ -862,7 +862,7 @@ (define_insn "subv2df3" [(set (match_operand:V2DF 0 "register_operand" "=v") - (minus:V2DF (match_operand:V2DF 1 "register_operand" "v") + (minus:V2DF (match_operand:V2DF 1 "register_operand" "%v") (match_operand:V2DF 2 "register_operand" "v")))] "TARGET_VX" "vfsdb\t%v0,%v1,%v2" @@ -870,7 +870,7 @@ (define_insn "mulv2df3" [(set (match_operand:V2DF 0 "register_operand" "=v") - (mult:V2DF (match_operand:V2DF 1 "register_operand" "v") + (mult:V2DF (match_operand:V2DF 1 "register_operand" "%v") (match_operand:V2DF 2 "register_operand" "v")))] "TARGET_VX" "vfmdb\t%v0,%v1,%v2" @@ -893,7 +893,7 @@ (define_insn "fmav2df4" [(set (match_operand:V2DF 0 "register_operand" "=v") - (fma:V2DF (match_operand:V2DF 1 "register_operand" "v") + (fma:V2DF (match_operand:V2DF 1 "register_operand" "%v") (match_operand:V2DF 2 "register_operand" "v") (match_operand:V2DF 3 "register_operand" "v")))] "TARGET_VX" @@ -902,7 +902,7 @@ (define_insn "fmsv2df4" [(set (match_operand:V2DF 0 "register_operand" "=v") - (fma:V2DF (match_operand:V2DF 1 "register_operand" "v") + (fma:V2DF (match_operand:V2DF 1 "register_operand" "%v") (match_operand:V2DF 2 "register_operand" "v") (neg:V2DF (match_operand:V2DF 3 "register_operand" "v"))))] "TARGET_VX" @@ -933,7 +933,7 @@ ; Emulate with compare + select (define_insn_and_split "smaxv2df3" [(set (match_operand:V2DF 0 "register_operand" "=v") - (smax:V2DF (match_operand:V2DF 1 "register_operand" "v") + (smax:V2DF (match_operand:V2DF 1 "register_operand" "%v") (match_operand:V2DF 2 "register_operand" "v")))] "TARGET_VX" "#" @@ -953,7 +953,7 @@ ; Emulate with compare + select (define_insn_and_split "sminv2df3" [(set (match_operand:V2DF 0 "register_operand" "=v") - (smin:V2DF (match_operand:V2DF 1 "register_operand" "v") + (smin:V2DF (match_operand:V2DF 1 "register_operand" "%v") (match_operand:V2DF 2 "register_operand" "v")))] "TARGET_VX" "#" diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index 65e683c972d..489bbeec22d 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -575,7 +575,7 @@ (define_insn "vec_addc" [(set (match_operand:VI_HW 0 "register_operand" "=v") - (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v") (match_operand:VI_HW 2 "register_operand" "v")] UNSPEC_VEC_ADDC))] "TARGET_VX" @@ -584,7 +584,7 @@ (define_insn "vec_addc_u128" [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "%v") (match_operand:V16QI 2 "register_operand" "v")] UNSPEC_VEC_ADDC_U128))] "TARGET_VX" @@ -596,7 +596,7 @@ (define_insn "vec_adde_u128" [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "%v") (match_operand:V16QI 2 "register_operand" "v") (match_operand:V16QI 3 "register_operand" "v")] UNSPEC_VEC_ADDE_U128))] @@ -609,7 +609,7 @@ (define_insn "vec_addec_u128" [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "%v") (match_operand:V16QI 2 "register_operand" "v") (match_operand:V16QI 3 "register_operand" "v")] UNSPEC_VEC_ADDEC_U128))] @@ -672,7 +672,7 @@ (define_insn "vec_avg" [(set (match_operand:VI_HW 0 "register_operand" "=v") - (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v") (match_operand:VI_HW 2 "register_operand" "v")] UNSPEC_VEC_AVG))] "TARGET_VX" @@ -683,7 +683,7 @@ (define_insn "vec_avgu" [(set (match_operand:VI_HW 0 "register_operand" "=v") - (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v") (match_operand:VI_HW 2 "register_operand" "v")] UNSPEC_VEC_AVGU))] "TARGET_VX" @@ -871,9 +871,9 @@ ; vmalb, vmalh, vmalf, vmalg (define_insn "vec_vmal" [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") - (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") - (match_operand:VI_HW_QHS 2 "register_operand" "v") - (match_operand:VI_HW_QHS 3 "register_operand" "v")] + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:VI_HW_QHS 3 "register_operand" "v")] UNSPEC_VEC_VMAL))] "TARGET_VX" "vmal\t%v0,%v1,%v2,%v3" @@ -884,9 +884,9 @@ ; vmahb; vmahh, vmahf, vmahg (define_insn "vec_vmah" [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") - (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") - (match_operand:VI_HW_QHS 2 "register_operand" "v") - (match_operand:VI_HW_QHS 3 "register_operand" "v")] + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:VI_HW_QHS 3 "register_operand" "v")] UNSPEC_VEC_VMAH))] "TARGET_VX" "vmah\t%v0,%v1,%v2,%v3" @@ -895,9 +895,9 @@ ; vmalhb; vmalhh, vmalhf, vmalhg (define_insn "vec_vmalh" [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") - (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") - (match_operand:VI_HW_QHS 2 "register_operand" "v") - (match_operand:VI_HW_QHS 3 "register_operand" "v")] + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:VI_HW_QHS 3 "register_operand" "v")] UNSPEC_VEC_VMALH))] "TARGET_VX" "vmalh\t%v0,%v1,%v2,%v3" @@ -908,8 +908,8 @@ ; vmaeb; vmaeh, vmaef, vmaeg (define_insn "vec_vmae" [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") - (match_operand:VI_HW_QHS 2 "register_operand" "v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "%v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") (match_operand: 3 "register_operand" "v")] UNSPEC_VEC_VMAE))] "TARGET_VX" @@ -919,7 +919,7 @@ ; vmaleb; vmaleh, vmalef, vmaleg (define_insn "vec_vmale" [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "%v") (match_operand:VI_HW_QHS 2 "register_operand" "v") (match_operand: 3 "register_operand" "v")] UNSPEC_VEC_VMALE))] @@ -932,7 +932,7 @@ ; vmaob; vmaoh, vmaof, vmaog (define_insn "vec_vmao" [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "%v") (match_operand:VI_HW_QHS 2 "register_operand" "v") (match_operand: 3 "register_operand" "v")] UNSPEC_VEC_VMAO))] @@ -959,7 +959,7 @@ ; vmhb, vmhh, vmhf (define_insn "vec_smulh" [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") - (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v") (match_operand:VI_HW_QHS 2 "register_operand" "v")] UNSPEC_VEC_SMULT_HI))] "TARGET_VX" @@ -969,7 +969,7 @@ ; vmlhb, vmlhh, vmlhf (define_insn "vec_umulh" [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") - (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v") (match_operand:VI_HW_QHS 2 "register_operand" "v")] UNSPEC_VEC_UMULT_HI))] "TARGET_VX" @@ -987,7 +987,7 @@ (define_insn "vec_nor3" [(set (match_operand:VT_HW 0 "register_operand" "=v") - (not:VT_HW (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "v") + (not:VT_HW (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "%v") (match_operand:VT_HW 2 "register_operand" "v"))))] "TARGET_VX" "vno\t%v0,%v1,%v2"