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config.gcc (mips64*-*-linux*): Handle mips64octeon*-*-linux*. 

* config.gcc (mips64*-*-linux*): Handle mips64octeon*-*-linux*.
	* config/mips/mips.h (enum processor_type): Add PROCESSOR_OCTEON.
	(TARGET_OCTEON): New macro.
	(TARGET_CPU_CPP_BUILTINS): Define __OCTEON__ for Octeon.
	(MIPS_ISA_LEVEL_SPEC, MIPS_ARCH_FLOAT_SPEC): Handle -march=octeon.
	(ISA_HAS_POP): New macro.
	* config/mips/driver-native.c (host_detect_local_cpu): Handle
	Octeon.
	* config/mips/mips.c (mips_cpu_info_table, mips_rtx_cost_data):
	Handle Octeon.
	* config/mips/mips.md (cpu): Add octeon.
	(type): Add pop attribute value.
	(popcount<mode>2): New pattern.
	* doc/invoke.texi (-march=@var{arch}): Add octeon.
testsuite/
	* gcc.target/mips/octeon-pop-1.c: New test.

From-SVN: r139554
This commit is contained in:
Adam Nemet 2008-08-25 00:57:01 +00:00 committed by Adam Nemet
parent 807e74dbc6
commit d97e6aca01
9 changed files with 88 additions and 5 deletions
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17
gcc/ChangeLog
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@ -1,3 +1,20 @@
2008-08-24 Adam Nemet <anemet@caviumnetworks.com>
* config.gcc (mips64*-*-linux*): Handle mips64octeon*-*-linux*.
* config/mips/mips.h (enum processor_type): Add PROCESSOR_OCTEON.
(TARGET_OCTEON): New macro.
(TARGET_CPU_CPP_BUILTINS): Define __OCTEON__ for Octeon.
(MIPS_ISA_LEVEL_SPEC, MIPS_ARCH_FLOAT_SPEC): Handle -march=octeon.
(ISA_HAS_POP): New macro.
* config/mips/driver-native.c (host_detect_local_cpu): Handle
Octeon.
* config/mips/mips.c (mips_cpu_info_table, mips_rtx_cost_data):
Handle Octeon.
* config/mips/mips.md (cpu): Add octeon.
(type): Add pop attribute value.
(popcount<mode>2): New pattern.
* doc/invoke.texi (-march=@var{arch}): Add octeon.
2008-08-24 Jan Hubicka <jh@suse.cz>
* doc/invoke.texi (-fipa-cp-clone): New option.

4
gcc/config.gcc
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@ -1551,6 +1551,10 @@ mips64*-*-linux* | mipsisa64*-*-linux*)
tm_file="${tm_file} mips/st.h"
tmake_file="${tmake_file} mips/t-st"
;;
mips64octeon*-*-linux*)
tm_defines="${tm_defines} MIPS_CPU_STRING_DEFAULT=\\\"octeon\\\""
target_cpu_default=MASK_SOFT_FLOAT_ABI
;;
mipsisa64r2*-*-linux*)
tm_defines="${tm_defines} MIPS_ISA_DEFAULT=65"
;;

2
gcc/config/mips/driver-native.c
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@ -67,6 +67,8 @@ host_detect_local_cpu (int argc, const char **argv)
cpu = "sb1";
else if (strstr (buf, "R5000") != NULL)
cpu = "r5000";
else if (strstr (buf, "Octeon") != NULL)
cpu = "octeon";
break;
}

15
gcc/config/mips/mips.c
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@ -652,7 +652,10 @@ static const struct mips_cpu_info mips_cpu_info_table[] = {
{ "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
{ "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
{ "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
{ "xlr", PROCESSOR_XLR, 64, 0 }
{ "xlr", PROCESSOR_XLR, 64, 0 },
/* MIPS64 Release 2 processors. */
{ "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
};
/* Default costs. If these are used for a processor we should look
@ -851,6 +854,16 @@ static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = {
},
{ /* M4k */
DEFAULT_COSTS
},
/* Octeon */
{
SOFT_FP_COSTS,
COSTS_N_INSNS (5), /* int_mult_si */
COSTS_N_INSNS (5), /* int_mult_di */
COSTS_N_INSNS (72), /* int_div_si */
COSTS_N_INSNS (72), /* int_div_di */
1, /* branch_cost */
4 /* memory_latency */
},
{ /* R3900 */
COSTS_N_INSNS (2), /* fp_add */

13
gcc/config/mips/mips.h
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@ -50,6 +50,7 @@ enum processor_type {
PROCESSOR_LOONGSON_2E,
PROCESSOR_LOONGSON_2F,
PROCESSOR_M4K,
PROCESSOR_OCTEON,
PROCESSOR_R3900,
PROCESSOR_R6000,
PROCESSOR_R4000,
@ -253,6 +254,7 @@ enum mips_code_readable_setting {
#define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
#define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
#define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
#define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
|| mips_arch == PROCESSOR_SB1A)
#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
@ -529,6 +531,10 @@ enum mips_code_readable_setting {
if (TARGET_LOONGSON_VECTORS) \
builtin_define ("__mips_loongson_vector_rev"); \
\
/* Historical Octeon macro. */ \
if (TARGET_OCTEON) \
builtin_define ("__OCTEON__"); \
\
/* Macros dependent on the C dialect. */ \
if (preprocessing_asm_p ()) \
{ \
@ -693,7 +699,7 @@ enum mips_code_readable_setting {
%{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
|march=34k*|march=74k*: -mips32r2} \
%{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
%{march=mips64r2: -mips64r2} \
%{march=mips64r2|march=octeon: -mips64r2} \
%{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
/* A spec that infers a -mhard-float or -msoft-float setting from an
@ -703,7 +709,7 @@ enum mips_code_readable_setting {
#define MIPS_ARCH_FLOAT_SPEC \
"%{mhard-float|msoft-float|march=mips*:; \
march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
|march=34kc|march=74kc|march=5kc: -msoft-float; \
|march=34kc|march=74kc|march=5kc|march=octeon: -msoft-float; \
march=*: -mhard-float}"
/* A spec condition that matches 32-bit options. It only works if
@ -996,6 +1002,9 @@ enum mips_code_readable_setting {
(target_flags_explicit & MASK_LLSC \
? TARGET_LLSC && !TARGET_MIPS16 \
: ISA_HAS_LL_SC)
/* ISA includes the pop instruction. */
#define ISA_HAS_POP TARGET_OCTEON
/* Add -G xx support. */

21
gcc/config/mips/mips.md
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@ -344,6 +344,7 @@
;; slt set less than instructions
;; signext sign extend instructions
;; clz the clz and clo instructions
;; pop the pop instruction
;; trap trap if instructions
;; imul integer multiply 2 operands
;; imul3 integer multiply 3 operands
@ -372,7 +373,7 @@
(define_attr "type"
"unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
shift,slt,signext,clz,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,
shift,slt,signext,clz,pop,trap,imul,imul3,imadd,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,
frsqrt2,multi,nop,ghost"
(cond [(eq_attr "jal" "!unset") (const_string "call")
@ -556,7 +557,7 @@
;; Attribute describing the processor. This attribute must match exactly
;; with the processor_type enumeration in mips.h.
(define_attr "cpu"
"r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000,xlr"
"r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf2_1,24kf1_1,74kc,74kf2_1,74kf1_1,74kf3_2,loongson_2e,loongson_2f,m4k,octeon,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000,xlr"
(const (symbol_ref "mips_tune")))
;; The type of hardware hazard associated with this instruction.
@ -2410,6 +2411,22 @@
"<d>clz\t%0,%1"
[(set_attr "type" "clz")
(set_attr "mode" "<MODE>")])
;;
;; ...................
;;
;; Count number of set bits.
;;
;; ...................
;;
(define_insn "popcount<mode>2"
[(set (match_operand:GPR 0 "register_operand" "=d")
(popcount:GPR (match_operand:GPR 1 "register_operand" "d")))]
"ISA_HAS_POP"
"<d>pop\t%0,%1"
[(set_attr "type" "pop")
(set_attr "mode" "<MODE>")])
;;
;; ....................

1
gcc/doc/invoke.texi
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@ -11999,6 +11999,7 @@ The processor names are:
@samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2},
@samp{loongson2e}, @samp{loongson2f},
@samp{m4k},
@samp{octeon},
@samp{orion},
@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
@samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000},

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2008-08-24 Adam Nemet <anemet@caviumnetworks.com>
* gcc.target/mips/octeon-pop-1.c: New test.
2008-08-24 Tobias Burnus <burnus@net-b.de>
PR fortran/37201

16
gcc/testsuite/gcc.target/mips/octeon-pop-1.c Normal file
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@ -0,0 +1,16 @@
/* { dg-do compile } */
/* { dg-mips-options "-O -march=octeon -mgp64" } */
/* { dg-final { scan-assembler "\tpop\t" } } */
/* { dg-final { scan-assembler "\tdpop\t" } } */
NOMIPS16 int
f (long long a)
{
return __builtin_popcountll (a);
}
NOMIPS16 int
g (int a)
{
return __builtin_popcount (a);
}