[AArch64] Implement <su><maxmin>v2di3 pattern
gcc/: PR target/63424 * config/aarch64/aarch64-simd.md (<su><maxmin>v2di3): New. gcc/testsuite/: PR target/63424 * gcc.target/aarch64/pr63424.c: New test. From-SVN: r217786
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@ -3,6 +3,11 @@
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* config/rs6000/constraints.md: Avoid signed integer overflows.
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* config/rs6000/constraints.md: Avoid signed integer overflows.
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* config/rs6000/predicates.md: Likewise.
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* config/rs6000/predicates.md: Likewise.
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2014-11-19 Renlin Li <Renlin.Li@arm.com>
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PR target/63424
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* config/aarch64/aarch64-simd.md (<su><maxmin>v2di3): New.
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2014-11-19 Renlin Li <Renlin.Li@arm.com>
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2014-11-19 Renlin Li <Renlin.Li@arm.com>
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PR middle-end/63762
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PR middle-end/63762
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@ -953,6 +953,39 @@
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[(set_attr "type" "neon_minmax<q>")]
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[(set_attr "type" "neon_minmax<q>")]
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)
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)
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(define_expand "<su><maxmin>v2di3"
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[(set (match_operand:V2DI 0 "register_operand" "")
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(MAXMIN:V2DI (match_operand:V2DI 1 "register_operand" "")
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(match_operand:V2DI 2 "register_operand" "")))]
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"TARGET_SIMD"
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{
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enum rtx_code cmp_operator;
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rtx cmp_fmt;
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switch (<CODE>)
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{
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case UMIN:
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cmp_operator = LTU;
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break;
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case SMIN:
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cmp_operator = LT;
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break;
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case UMAX:
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cmp_operator = GTU;
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break;
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case SMAX:
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cmp_operator = GT;
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break;
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default:
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gcc_unreachable ();
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}
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cmp_fmt = gen_rtx_fmt_ee (cmp_operator, V2DImode, operands[1], operands[2]);
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emit_insn (gen_aarch64_vcond_internalv2div2di (operands[0], operands[1],
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operands[2], cmp_fmt, operands[1], operands[2]));
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DONE;
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})
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;; vec_concat gives a new vector with the low elements from operand 1, and
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;; vec_concat gives a new vector with the low elements from operand 1, and
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;; the high elements from operand 2. That is to say, given op1 = { a, b }
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;; the high elements from operand 2. That is to say, given op1 = { a, b }
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;; op2 = { c, d }, vec_concat (op1, op2) = { a, b, c, d }.
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;; op2 = { c, d }, vec_concat (op1, op2) = { a, b, c, d }.
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@ -1,3 +1,7 @@
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2014-11-19 Renlin Li <Renlin.Li@arm.com>
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PR target/63424
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* gcc.target/aarch64/pr63424.c: New test.
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2014-11-19 Renlin Li <Renlin.Li@arm.com>
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2014-11-19 Renlin Li <Renlin.Li@arm.com>
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PR middle-end/63762
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PR middle-end/63762
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@ -0,0 +1,39 @@
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/* { dg-do compile } */
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/* { dg-options "-O3" } */
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#include <stdint.h>
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uint32_t
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truncate_int (const unsigned long long value)
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{
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if ( value < 0 )
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{
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return 0;
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}
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else if ( value > UINT32_MAX )
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{
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return UINT32_MAX;
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}
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else
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return (uint32_t)value;
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}
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uint32_t
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mul (const unsigned long long x, const unsigned long long y)
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{
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uint32_t value = truncate_int (x * y);
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return value;
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}
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uint32_t *
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test(unsigned size, uint32_t *a, uint32_t s)
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{
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unsigned i;
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for (i = 0; i < size; i++)
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{
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a[i] = mul (a[i], s);
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}
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return a;
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}
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