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re PR target/47715 ([x32] TLS doesn't work) 

PR target/47715
	* config/i386/i386.md (*load_tp_x32): New.
	(*load_tp_x32_zext): Ditto.
	(*add_tp_x32): Ditto.
	(*add_tp_x32_zext): Ditto.
	(*load_tp_<mode>): Disable for TARGET_X32 targets.
	(*add_tp_<mode>): Ditto.
	* config/i386/i386.c (get_thread_pointer): Load thread pointer in
	ptr_mode and convert to Pmode if needed.

From-SVN: r176924
This commit is contained in:
Uros Bizjak 2011-07-29 15:48:40 +02:00 committed by Uros Bizjak
parent db7ccee202
commit dadecee203
4 changed files with 81 additions and 12 deletions
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16
gcc/ChangeLog
View File

@ -1,5 +1,17 @@
2011-07-29 Uros Bizjak <ubizjak@gmail.com>
PR target/47715
* config/i386/i386.md (*load_tp_x32): New.
(*load_tp_x32_zext): Ditto.
(*add_tp_x32): Ditto.
(*add_tp_x32_zext): Ditto.
(*load_tp_<mode>): Disable for TARGET_X32 targets.
(*add_tp_<mode>): Ditto.
* config/i386/i386.c (get_thread_pointer): Load thread pointer in
ptr_mode and convert to Pmode if needed.
2011-07-29 Georg-Johann Lay <avr@gjlay.de>
PR target/49687
* config/avr/avr.md (mulsi3, *mulsi3, mulu<mode>si3,
muls<mode>si3, mulohisi3, mulhisi3, umulhisi3, usmulhisi3,
@ -18,7 +30,7 @@
are not suitable.
2011-07-29 Georg-Johann Lay <avr@gjlay.de>
PR target/49313
* config/avr/libgcc.S (__ffshi2): Don't skip 2-word instruction.
(__ctzsi2): Result for 0 may be undefined.

14
gcc/config/i386/i386.c
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@ -12118,17 +12118,15 @@ legitimize_pic_address (rtx orig, rtx reg)
static rtx
get_thread_pointer (bool to_reg)
{
rtx tp, reg, insn;
rtx tp = gen_rtx_UNSPEC (ptr_mode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
if (!to_reg)
return tp;
if (GET_MODE (tp) != Pmode)
tp = convert_to_mode (Pmode, tp, 1);
reg = gen_reg_rtx (Pmode);
insn = gen_rtx_SET (VOIDmode, reg, tp);
insn = emit_insn (insn);
if (to_reg)
tp = copy_addr_to_reg (tp);
return reg;
return tp;
}
/* Construct the SYMBOL_REF for the tls_get_addr function. */

53
gcc/config/i386/i386.md
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@ -12444,10 +12444,32 @@
(define_mode_attr tp_seg [(SI "gs") (DI "fs")])
;; Load and add the thread base pointer from %<tp_seg>:0.
(define_insn "*load_tp_x32"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(const_int 0)] UNSPEC_TP))]
"TARGET_X32"
"mov{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}"
[(set_attr "type" "imov")
(set_attr "modrm" "0")
(set_attr "length" "7")
(set_attr "memory" "load")
(set_attr "imm_disp" "false")])
(define_insn "*load_tp_x32_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (unspec:SI [(const_int 0)] UNSPEC_TP)))]
"TARGET_X32"
"mov{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}"
[(set_attr "type" "imov")
(set_attr "modrm" "0")
(set_attr "length" "7")
(set_attr "memory" "load")
(set_attr "imm_disp" "false")])
(define_insn "*load_tp_<mode>"
[(set (match_operand:P 0 "register_operand" "=r")
(unspec:P [(const_int 0)] UNSPEC_TP))]
""
"!TARGET_X32"
"mov{<imodesuffix>}\t{%%<tp_seg>:0, %0|%0, <iptrsize> PTR <tp_seg>:0}"
[(set_attr "type" "imov")
(set_attr "modrm" "0")
@ -12455,12 +12477,39 @@
(set_attr "memory" "load")
(set_attr "imm_disp" "false")])
(define_insn "*add_tp_x32"
[(set (match_operand:SI 0 "register_operand" "=r")
(plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
(match_operand:SI 1 "register_operand" "0")))
(clobber (reg:CC FLAGS_REG))]
"TARGET_X32"
"add{l}\t{%%fs:0, %0|%0, DWORD PTR fs:0}"
[(set_attr "type" "alu")
(set_attr "modrm" "0")
(set_attr "length" "7")
(set_attr "memory" "load")
(set_attr "imm_disp" "false")])
(define_insn "*add_tp_x32_zext"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI
(plus:SI (unspec:SI [(const_int 0)] UNSPEC_TP)
(match_operand:SI 1 "register_operand" "0"))))
(clobber (reg:CC FLAGS_REG))]
"TARGET_X32"
"add{l}\t{%%fs:0, %k0|%k0, DWORD PTR fs:0}"
[(set_attr "type" "alu")
(set_attr "modrm" "0")
(set_attr "length" "7")
(set_attr "memory" "load")
(set_attr "imm_disp" "false")])
(define_insn "*add_tp_<mode>"
[(set (match_operand:P 0 "register_operand" "=r")
(plus:P (unspec:P [(const_int 0)] UNSPEC_TP)
(match_operand:P 1 "register_operand" "0")))
(clobber (reg:CC FLAGS_REG))]
""
"!TARGET_X32"
"add{<imodesuffix>}\t{%%<tp_seg>:0, %0|%0, <iptrsize> PTR <tp_seg>:0}"
[(set_attr "type" "alu")
(set_attr "modrm" "0")

10
gcc/function.c
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@ -4570,9 +4570,14 @@ stack_protect_prologue (void)
tree guard_decl = targetm.stack_protect_guard ();
rtx x, y;
printf ("TESTx\n");
x = expand_normal (crtl->stack_protect_guard);
y = expand_normal (guard_decl);
debug_rtx (x);
debug_rtx (y);
/* Allow the target to copy from Y to X without leaking Y into a
register. */
if (HAVE_stack_protect_set)
@ -4604,9 +4609,14 @@ stack_protect_epilogue (void)
rtx label = gen_label_rtx ();
rtx x, y, tmp;
printf ("TESTz\n");
x = expand_normal (crtl->stack_protect_guard);
y = expand_normal (guard_decl);
debug_rtx (x);
debug_rtx (y);
/* Allow the target to compare Y with X without leaking either into
a register. */
switch (HAVE_stack_protect_test != 0)