[AArch64] Fix layout of frame layout code.
From-SVN: r211416
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@ -1,3 +1,8 @@
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2014-06-10 Jiong Wang <jiong.wang@arm.com>
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* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs)
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(aarch64_save_or_restore_callee_save_registers): Fix layout.
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2014-06-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/aarch64/aarch64-simd.md (aarch64_sqdmulh_lane<mode>):
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@ -1917,7 +1917,6 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
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rtx (*gen_mem_ref)(enum machine_mode, rtx)
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= (frame_pointer_needed)? gen_frame_mem : gen_rtx_MEM;
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for (regno = V0_REGNUM; regno <= V31_REGNUM; regno++)
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{
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if (aarch64_register_saved_on_entry (regno))
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@ -1935,10 +1934,12 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
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{
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/* Empty loop. */
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}
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if (regno2 <= V31_REGNUM &&
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aarch64_register_saved_on_entry (regno2))
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{
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rtx mem2;
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/* Next highest register to be saved. */
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mem2 = gen_mem_ref (DFmode,
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plus_constant
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@ -1964,10 +1965,10 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
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gen_rtx_REG (DFmode, regno2));
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}
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/* The first part of a frame-related parallel insn
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is always assumed to be relevant to the frame
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calculations; subsequent parts, are only
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frame-related if explicitly marked. */
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/* The first part of a frame-related parallel insn is
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always assumed to be relevant to the frame
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calculations; subsequent parts, are only
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frame-related if explicitly marked. */
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RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
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regno = regno2;
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start_offset += increment * 2;
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@ -1987,7 +1988,6 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
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RTX_FRAME_RELATED_P (insn) = 1;
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}
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}
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}
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@ -1995,7 +1995,7 @@ aarch64_save_or_restore_fprs (int start_offset, int increment,
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restore's have to happen. */
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static void
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aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
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bool restore)
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bool restore)
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{
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rtx insn;
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rtx base_rtx = stack_pointer_rtx;
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@ -2027,6 +2027,7 @@ aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
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aarch64_register_saved_on_entry (regno2))
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{
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rtx mem2;
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/* Next highest register to be saved. */
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mem2 = gen_mem_ref (Pmode,
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plus_constant
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@ -2050,12 +2051,11 @@ aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
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add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, regno2));
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}
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/* The first part of a frame-related parallel insn
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is always assumed to be relevant to the frame
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calculations; subsequent parts, are only
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frame-related if explicitly marked. */
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RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0,
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1)) = 1;
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/* The first part of a frame-related parallel insn is
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always assumed to be relevant to the frame
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calculations; subsequent parts, are only
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frame-related if explicitly marked. */
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RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
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regno = regno2;
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start_offset += increment * 2;
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}
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@ -2075,7 +2075,6 @@ aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT offset,
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}
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aarch64_save_or_restore_fprs (start_offset, increment, restore, base_rtx);
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}
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/* AArch64 stack frames generated by this compiler look like:
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