[AArch64_BE 2/4] Big-Endian lane numbering fix
2013-01-23 Alex Velenko <Alex.Velenko@arm.com> * config/aarch64/aarch64-simd.md (aarch64_be_checked_get_lane<mode>): New define_expand. * config/aarch64/aarch64-simd-builtins.def (BUILTIN_VALL (GETLANE, be_checked_get_lane, 0): New builtin definition. * config/aarch64/arm_neon.h: (__aarch64_vget_lane_any): Use new safe be builtin. From-SVN: r206970
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@ -1,3 +1,13 @@
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2013-01-23 Alex Velenko <Alex.Velenko@arm.com>
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* config/aarch64/aarch64-simd.md
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(aarch64_be_checked_get_lane<mode>): New define_expand.
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* config/aarch64/aarch64-simd-builtins.def
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(BUILTIN_VALL (GETLANE, be_checked_get_lane, 0):
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New builtin definition.
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* config/aarch64/arm_neon.h: (__aarch64_vget_lane_any):
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Use new safe be builtin.
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2014-01-23 Alex Velenko <Alex.Velenko@arm.com>
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* config/aarch64/aarch64-simd.md (aarch64_be_ld1<mode>):
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@ -49,6 +49,7 @@
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BUILTIN_VALL (GETLANE, get_lane, 0)
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VAR1 (GETLANE, get_lane, 0, di)
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BUILTIN_VALL (GETLANE, be_checked_get_lane, 0)
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BUILTIN_VD_RE (REINTERP, reinterpretdi, 0)
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BUILTIN_VDC (REINTERP, reinterpretv8qi, 0)
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@ -2062,6 +2062,20 @@
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[(set_attr "type" "neon_to_gp<q>")]
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)
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(define_expand "aarch64_be_checked_get_lane<mode>"
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[(match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand")
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(match_operand:VALL 1 "register_operand")
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(match_operand:SI 2 "immediate_operand")]
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"TARGET_SIMD"
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{
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operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
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emit_insn (gen_aarch64_get_lane<mode> (operands[0],
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operands[1],
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operands[2]));
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DONE;
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}
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)
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;; Lane extraction of a value, neither sign nor zero extension
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;; is guaranteed so upper bits should be considered undefined.
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(define_insn "aarch64_get_lane<mode>"
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@ -457,7 +457,7 @@ typedef struct poly16x8x4_t
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#define __aarch64_vget_lane_any(__size, __cast_ret, __cast_a, __a, __b) \
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(__cast_ret \
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__builtin_aarch64_get_lane##__size (__cast_a __a, __b))
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__builtin_aarch64_be_checked_get_lane##__size (__cast_a __a, __b))
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#define __aarch64_vget_lane_f32(__a, __b) \
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__aarch64_vget_lane_any (v2sf, , , __a, __b)
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