re PR target/49687 ([avr] Missed optimization for widening MUL)
PR target/49687 * config/avr/avr.md (mulsi3, *mulsi3, mulu<mode>si3, muls<mode>si3, mulohisi3, mulhisi3, umulhisi3, usmulhisi3, *<any_extend:extend_prefix><any_extend2:extend_prefix>mul<QIHI:mode><QIHI2:mode>si3): Add X to register footprint: Clobber r26/r27. From-SVN: r176923
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@ -1,3 +1,11 @@
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2011-07-29 Georg-Johann Lay <avr@gjlay.de>
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PR target/49687
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* config/avr/avr.md (mulsi3, *mulsi3, mulu<mode>si3,
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muls<mode>si3, mulohisi3, mulhisi3, umulhisi3, usmulhisi3,
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*<any_extend:extend_prefix><any_extend2:extend_prefix>mul<QIHI:mode><QIHI2:mode>si3):
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Add X to register footprint: Clobber r26/r27.
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2011-07-29 Richard Guenther <rguenther@suse.de>
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2011-07-29 Richard Guenther <rguenther@suse.de>
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* builtins.c (fold_builtin_signbit): Build the comparison
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* builtins.c (fold_builtin_signbit): Build the comparison
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@ -1373,6 +1373,7 @@
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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(mult:SI (match_operand:SI 1 "register_operand" "")
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(mult:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")))
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(match_operand:SI 2 "nonmemory_operand" "")))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))])]
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(clobber (reg:DI 18))])]
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"AVR_HAVE_MUL"
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"AVR_HAVE_MUL"
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{
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{
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@ -1395,6 +1396,7 @@
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[(set (match_operand:SI 0 "pseudo_register_operand" "=r")
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[(set (match_operand:SI 0 "pseudo_register_operand" "=r")
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(mult:SI (match_operand:SI 1 "pseudo_register_operand" "r")
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(mult:SI (match_operand:SI 1 "pseudo_register_operand" "r")
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(match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
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(match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))]
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(clobber (reg:DI 18))]
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"AVR_HAVE_MUL && !reload_completed"
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"AVR_HAVE_MUL && !reload_completed"
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{ gcc_unreachable(); }
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{ gcc_unreachable(); }
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@ -1431,6 +1433,7 @@
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[(set (match_operand:SI 0 "pseudo_register_operand" "=r")
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[(set (match_operand:SI 0 "pseudo_register_operand" "=r")
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(mult:SI (zero_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
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(mult:SI (zero_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
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(match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
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(match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))]
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(clobber (reg:DI 18))]
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"AVR_HAVE_MUL && !reload_completed"
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"AVR_HAVE_MUL && !reload_completed"
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{ gcc_unreachable(); }
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{ gcc_unreachable(); }
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@ -1466,6 +1469,7 @@
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[(set (match_operand:SI 0 "pseudo_register_operand" "=r")
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[(set (match_operand:SI 0 "pseudo_register_operand" "=r")
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(mult:SI (sign_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
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(mult:SI (sign_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
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(match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
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(match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))]
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(clobber (reg:DI 18))]
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"AVR_HAVE_MUL && !reload_completed"
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"AVR_HAVE_MUL && !reload_completed"
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{ gcc_unreachable(); }
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{ gcc_unreachable(); }
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@ -1509,6 +1513,7 @@
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(mult:SI (not:SI (zero_extend:SI
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(mult:SI (not:SI (zero_extend:SI
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(not:HI (match_operand:HI 1 "pseudo_register_operand" "r"))))
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(not:HI (match_operand:HI 1 "pseudo_register_operand" "r"))))
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(match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
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(match_operand:SI 2 "pseudo_register_or_const_int_operand" "rn")))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))]
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(clobber (reg:DI 18))]
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"AVR_HAVE_MUL && !reload_completed"
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"AVR_HAVE_MUL && !reload_completed"
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{ gcc_unreachable(); }
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{ gcc_unreachable(); }
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@ -1528,6 +1533,7 @@
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
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(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
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(sign_extend:SI (match_operand:HI 2 "register_operand" ""))))
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(sign_extend:SI (match_operand:HI 2 "register_operand" ""))))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))])]
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(clobber (reg:DI 18))])]
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"AVR_HAVE_MUL"
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"AVR_HAVE_MUL"
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"")
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"")
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@ -1536,6 +1542,7 @@
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
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(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
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(zero_extend:SI (match_operand:HI 2 "register_operand" ""))))
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(zero_extend:SI (match_operand:HI 2 "register_operand" ""))))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))])]
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(clobber (reg:DI 18))])]
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"AVR_HAVE_MUL"
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"AVR_HAVE_MUL"
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"")
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"")
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@ -1544,6 +1551,7 @@
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
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(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" ""))
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(sign_extend:SI (match_operand:HI 2 "register_operand" ""))))
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(sign_extend:SI (match_operand:HI 2 "register_operand" ""))))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))])]
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(clobber (reg:DI 18))])]
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"AVR_HAVE_MUL"
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"AVR_HAVE_MUL"
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"")
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"")
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@ -1557,6 +1565,7 @@
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[(set (match_operand:SI 0 "pseudo_register_operand" "=r")
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[(set (match_operand:SI 0 "pseudo_register_operand" "=r")
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(mult:SI (any_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
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(mult:SI (any_extend:SI (match_operand:QIHI 1 "pseudo_register_operand" "r"))
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(any_extend2:SI (match_operand:QIHI2 2 "pseudo_register_operand" "r"))))
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(any_extend2:SI (match_operand:QIHI2 2 "pseudo_register_operand" "r"))))
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(clobber (reg:HI 26))
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(clobber (reg:DI 18))]
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(clobber (reg:DI 18))]
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"AVR_HAVE_MUL && !reload_completed"
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"AVR_HAVE_MUL && !reload_completed"
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{ gcc_unreachable(); }
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{ gcc_unreachable(); }
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