aarch64: Model zero-high-half semantics of ADDHN/SUBHN instructions
Model the zero-high-half semantics of the narrowing arithmetic Neon instructions in the aarch64_<sur><addsub>hn<mode> RTL pattern. Modeling these semantics allows for better RTL combinations while also removing some register allocation issues as the compiler now knows that the operation is totally destructive. Add new tests to narrow_zero_high_half.c to verify the benefit of this change. gcc/ChangeLog: 2021-06-14 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd.md (aarch64_<sur><addsub>hn<mode>): Change to an expander that emits the correct instruction depending on endianness. (aarch64_<sur><addsub>hn<mode>_insn_le): Define. (aarch64_<sur><addsub>hn<mode>_insn_be): Define. gcc/testsuite/ChangeLog: * gcc.target/aarch64/narrow_zero_high_half.c: Add new tests.
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Jonathan Wright
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@ -4661,16 +4661,53 @@
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;; <r><addsub>hn<q>.
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(define_insn "aarch64_<sur><addsub>hn<mode>"
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[(set (match_operand:<VNARROWQ> 0 "register_operand" "=w")
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(unspec:<VNARROWQ> [(match_operand:VQN 1 "register_operand" "w")
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(match_operand:VQN 2 "register_operand" "w")]
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ADDSUBHN))]
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"TARGET_SIMD"
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(define_insn "aarch64_<sur><addsub>hn<mode>_insn_le"
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[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
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(vec_concat:<VNARROWQ2>
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(unspec:<VNARROWQ> [(match_operand:VQN 1 "register_operand" "w")
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(match_operand:VQN 2 "register_operand" "w")]
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ADDSUBHN)
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(match_operand:<VNARROWQ> 3 "aarch64_simd_or_scalar_imm_zero")))]
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"TARGET_SIMD && !BYTES_BIG_ENDIAN"
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"<sur><addsub>hn\\t%0.<Vntype>, %1.<Vtype>, %2.<Vtype>"
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[(set_attr "type" "neon_<addsub>_halve_narrow_q")]
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)
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(define_insn "aarch64_<sur><addsub>hn<mode>_insn_be"
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[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
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(vec_concat:<VNARROWQ2>
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(match_operand:<VNARROWQ> 3 "aarch64_simd_or_scalar_imm_zero")
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(unspec:<VNARROWQ> [(match_operand:VQN 1 "register_operand" "w")
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(match_operand:VQN 2 "register_operand" "w")]
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ADDSUBHN)))]
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"TARGET_SIMD && BYTES_BIG_ENDIAN"
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"<sur><addsub>hn\\t%0.<Vntype>, %1.<Vtype>, %2.<Vtype>"
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[(set_attr "type" "neon_<addsub>_halve_narrow_q")]
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)
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(define_expand "aarch64_<sur><addsub>hn<mode>"
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[(set (match_operand:<VNARROWQ> 0 "register_operand")
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(unspec:<VNARROWQ> [(match_operand:VQN 1 "register_operand")
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(match_operand:VQN 2 "register_operand")]
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ADDSUBHN))]
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"TARGET_SIMD"
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{
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rtx tmp = gen_reg_rtx (<VNARROWQ2>mode);
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_aarch64_<sur><addsub>hn<mode>_insn_be (tmp, operands[1],
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operands[2], CONST0_RTX (<VNARROWQ>mode)));
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else
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emit_insn (gen_aarch64_<sur><addsub>hn<mode>_insn_le (tmp, operands[1],
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operands[2], CONST0_RTX (<VNARROWQ>mode)));
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/* The intrinsic expects a narrow result, so emit a subreg that will get
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optimized away as appropriate. */
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emit_move_insn (operands[0], lowpart_subreg (<VNARROWQ>mode, tmp,
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<VNARROWQ2>mode));
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DONE;
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}
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)
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(define_insn "aarch64_<sur><addsub>hn2<mode>_insn_le"
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[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
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(vec_concat:<VNARROWQ2>
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@ -74,6 +74,42 @@ TEST_UNARY (vqmovn, uint8x16_t, uint16x8_t, u16, u8)
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TEST_UNARY (vqmovn, uint16x8_t, uint32x4_t, u32, u16)
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TEST_UNARY (vqmovn, uint32x4_t, uint64x2_t, u64, u32)
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#define TEST_ARITH(name, rettype, intype, fs, rs) \
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rettype test_ ## name ## _ ## fs ## _zero_high \
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(intype a, intype b) \
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{ \
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return vcombine_ ## rs (name ## _ ## fs (a, b), \
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vdup_n_ ## rs (0)); \
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}
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TEST_ARITH (vaddhn, int8x16_t, int16x8_t, s16, s8)
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TEST_ARITH (vaddhn, int16x8_t, int32x4_t, s32, s16)
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TEST_ARITH (vaddhn, int32x4_t, int64x2_t, s64, s32)
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TEST_ARITH (vaddhn, uint8x16_t, uint16x8_t, u16, u8)
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TEST_ARITH (vaddhn, uint16x8_t, uint32x4_t, u32, u16)
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TEST_ARITH (vaddhn, uint32x4_t, uint64x2_t, u64, u32)
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TEST_ARITH (vraddhn, int8x16_t, int16x8_t, s16, s8)
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TEST_ARITH (vraddhn, int16x8_t, int32x4_t, s32, s16)
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TEST_ARITH (vraddhn, int32x4_t, int64x2_t, s64, s32)
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TEST_ARITH (vraddhn, uint8x16_t, uint16x8_t, u16, u8)
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TEST_ARITH (vraddhn, uint16x8_t, uint32x4_t, u32, u16)
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TEST_ARITH (vraddhn, uint32x4_t, uint64x2_t, u64, u32)
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TEST_ARITH (vsubhn, int8x16_t, int16x8_t, s16, s8)
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TEST_ARITH (vsubhn, int16x8_t, int32x4_t, s32, s16)
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TEST_ARITH (vsubhn, int32x4_t, int64x2_t, s64, s32)
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TEST_ARITH (vsubhn, uint8x16_t, uint16x8_t, u16, u8)
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TEST_ARITH (vsubhn, uint16x8_t, uint32x4_t, u32, u16)
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TEST_ARITH (vsubhn, uint32x4_t, uint64x2_t, u64, u32)
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TEST_ARITH (vrsubhn, int8x16_t, int16x8_t, s16, s8)
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TEST_ARITH (vrsubhn, int16x8_t, int32x4_t, s32, s16)
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TEST_ARITH (vrsubhn, int32x4_t, int64x2_t, s64, s32)
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TEST_ARITH (vrsubhn, uint8x16_t, uint16x8_t, u16, u8)
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TEST_ARITH (vrsubhn, uint16x8_t, uint32x4_t, u32, u16)
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TEST_ARITH (vrsubhn, uint32x4_t, uint64x2_t, u64, u32)
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/* { dg-final { scan-assembler-not "dup\\t" } } */
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/* { dg-final { scan-assembler-times "\\tshrn\\tv" 6} } */
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@ -88,3 +124,7 @@ TEST_UNARY (vqmovn, uint32x4_t, uint64x2_t, u64, u32)
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/* { dg-final { scan-assembler-times "\\tsqxtun\\tv" 3} } */
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/* { dg-final { scan-assembler-times "\\tuqxtn\\tv" 3} } */
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/* { dg-final { scan-assembler-times "\\tsqxtn\\tv" 3} } */
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/* { dg-final { scan-assembler-times "\\taddhn\\tv" 6} } */
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/* { dg-final { scan-assembler-times "\\tsubhn\\tv" 6} } */
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/* { dg-final { scan-assembler-times "\\trsubhn\\tv" 6} } */
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/* { dg-final { scan-assembler-times "\\traddhn\\tv" 6} } */
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