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Remove AND_HARD_REG_SET 

Use "x &= y" instead of "AND_HARD_REG_SET (x, y)" (or just "x & y"
if the result is a temporary).

2019-09-09  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* hard-reg-set.h (HARD_REG_SET::operator&): New function.
	(HARD_REG_SET::operator&): Likewise.
	(AND_HARD_REG_SET): Delete.
	* caller-save.c (setup_save_areas): Use "&" instead of
	AND_HARD_REG_SET.
	(save_call_clobbered_regs): Likewise.
	* config/gcn/gcn.c (gcn_md_reorg): Likewise.
	* config/m32c/m32c.c (reduce_class): Likewise.
	* config/rs6000/rs6000.c (rs6000_register_move_cost): Likewise.
	* final.c (get_call_reg_set_usage): Likewise.
	* ira-color.c (add_allocno_hard_regs_to_forest): Likewise.
	(setup_left_conflict_sizes_p): Likewise.
	* ira-conflicts.c (print_allocno_conflicts): Likewise.
	(ira_build_conflicts): Likewise.
	* ira-costs.c (restrict_cost_classes): Likewise.
	* ira.c (setup_stack_reg_pressure_class, setup_class_translate_array)
	(setup_reg_class_relations): Likewise.
	* reginfo.c (init_reg_sets_1, record_subregs_of_mode): Likewise.
	* reload1.c (maybe_fix_stack_asms, finish_spills): Likewise.
	* resource.c (find_dead_or_set_registers): Likewise.
	* sel-sched.c (mark_unavailable_hard_regs): Likewise.

From-SVN: r275530
This commit is contained in:
Richard Sandiford 2019-09-09 17:59:14 +00:00 committed by Richard Sandiford
parent 50b3f54d55
commit dc333d8ff6
15 changed files with 73 additions and 60 deletions
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24
gcc/ChangeLog
View File

@ -1,3 +1,27 @@
2019-09-09 Richard Sandiford <richard.sandiford@arm.com>
* hard-reg-set.h (HARD_REG_SET::operator&): New function.
(HARD_REG_SET::operator&): Likewise.
(AND_HARD_REG_SET): Delete.
* caller-save.c (setup_save_areas): Use "&" instead of
AND_HARD_REG_SET.
(save_call_clobbered_regs): Likewise.
* config/gcn/gcn.c (gcn_md_reorg): Likewise.
* config/m32c/m32c.c (reduce_class): Likewise.
* config/rs6000/rs6000.c (rs6000_register_move_cost): Likewise.
* final.c (get_call_reg_set_usage): Likewise.
* ira-color.c (add_allocno_hard_regs_to_forest): Likewise.
(setup_left_conflict_sizes_p): Likewise.
* ira-conflicts.c (print_allocno_conflicts): Likewise.
(ira_build_conflicts): Likewise.
* ira-costs.c (restrict_cost_classes): Likewise.
* ira.c (setup_stack_reg_pressure_class, setup_class_translate_array)
(setup_reg_class_relations): Likewise.
* reginfo.c (init_reg_sets_1, record_subregs_of_mode): Likewise.
* reload1.c (maybe_fix_stack_asms, finish_spills): Likewise.
* resource.c (find_dead_or_set_registers): Likewise.
* sel-sched.c (mark_unavailable_hard_regs): Likewise.
2019-09-09 Richard Sandiford <richard.sandiford@arm.com>
* hard-reg-set.h (HARD_REG_SET::operator~): New function.

8
gcc/caller-save.c
View File

@ -457,7 +457,7 @@ setup_save_areas (void)
AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set);
AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets);
AND_HARD_REG_SET (hard_regs_to_save, used_regs);
hard_regs_to_save &= used_regs;
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
if (TEST_HARD_REG_BIT (hard_regs_to_save, regno))
{
@ -542,7 +542,7 @@ setup_save_areas (void)
AND_COMPL_HARD_REG_SET (used_regs, call_fixed_reg_set);
AND_COMPL_HARD_REG_SET (used_regs, this_insn_sets);
AND_HARD_REG_SET (hard_regs_to_save, used_regs);
hard_regs_to_save &= used_regs;
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
if (TEST_HARD_REG_BIT (hard_regs_to_save, regno))
{
@ -781,7 +781,7 @@ save_call_clobbered_regs (void)
CLEAR_HARD_REG_SET (referenced_regs);
mark_referenced_regs (&PATTERN (insn),
mark_reg_as_referenced, NULL);
AND_HARD_REG_SET (referenced_regs, hard_regs_saved);
referenced_regs &= hard_regs_saved;
}
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
@ -857,7 +857,7 @@ save_call_clobbered_regs (void)
AND_COMPL_HARD_REG_SET (hard_regs_to_save, hard_regs_saved);
get_call_reg_set_usage (insn, &call_def_reg_set,
call_used_reg_set);
AND_HARD_REG_SET (hard_regs_to_save, call_def_reg_set);
hard_regs_to_save &= call_def_reg_set;
for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
if (TEST_HARD_REG_BIT (hard_regs_to_save, regno))

12
gcc/config/gcn/gcn.c
View File

@ -4552,9 +4552,7 @@ gcn_md_reorg (void)
&& prev_insn->unit == UNIT_VECTOR
&& gcn_vmem_insn_p (itype))
{
HARD_REG_SET regs;
regs = prev_insn->writes;
AND_HARD_REG_SET (regs, ireads);
HARD_REG_SET regs = prev_insn->writes & ireads;
if (hard_reg_set_intersect_p
(regs, reg_class_contents[(int) SGPR_REGS]))
nops_rqd = 5 - prev_insn->age;
@ -4582,9 +4580,7 @@ gcn_md_reorg (void)
&& prev_insn->unit == UNIT_VECTOR
&& get_attr_laneselect (insn) == LANESELECT_YES)
{
HARD_REG_SET regs;
regs = prev_insn->writes;
AND_HARD_REG_SET (regs, ireads);
HARD_REG_SET regs = prev_insn->writes & ireads;
if (hard_reg_set_intersect_p
(regs, reg_class_contents[(int) SGPR_REGS])
|| hard_reg_set_intersect_p
@ -4598,9 +4594,7 @@ gcn_md_reorg (void)
&& prev_insn->unit == UNIT_VECTOR
&& itype == TYPE_VOP_DPP)
{
HARD_REG_SET regs;
regs = prev_insn->writes;
AND_HARD_REG_SET (regs, ireads);
HARD_REG_SET regs = prev_insn->writes & ireads;
if (hard_reg_set_intersect_p
(regs, reg_class_contents[(int) VGPR_REGS]))
nops_rqd = 2 - prev_insn->age;

3
gcc/config/m32c/m32c.c
View File

@ -341,8 +341,7 @@ reduce_class (reg_class_t original_class, reg_class_t limiting_class,
if (original_class == limiting_class)
return original_class;
cc = reg_class_contents[original_class];
AND_HARD_REG_SET (cc, reg_class_contents[limiting_class]);
cc = reg_class_contents[original_class] & reg_class_contents[limiting_class];
for (i = 0; i < LIM_REG_CLASSES; i++)
{

6
gcc/config/rs6000/rs6000.c
View File

@ -21107,10 +21107,8 @@ rs6000_register_move_cost (machine_mode mode,
Do this first so we give best-case answers for union classes
containing both gprs and vsx regs. */
HARD_REG_SET to_vsx, from_vsx;
to_vsx = reg_class_contents[to];
AND_HARD_REG_SET (to_vsx, reg_class_contents[VSX_REGS]);
from_vsx = reg_class_contents[from];
AND_HARD_REG_SET (from_vsx, reg_class_contents[VSX_REGS]);
to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS];
from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS];
if (!hard_reg_set_empty_p (to_vsx)
&& !hard_reg_set_empty_p (from_vsx)
&& (TARGET_VSX

3
gcc/final.c
View File

@ -5090,8 +5090,7 @@ get_call_reg_set_usage (rtx_insn *insn, HARD_REG_SET *reg_set,
if (node != NULL
&& node->function_used_regs_valid)
{
*reg_set = node->function_used_regs;
AND_HARD_REG_SET (*reg_set, default_set);
*reg_set = node->function_used_regs & default_set;
return true;
}
}

33
gcc/hard-reg-set.h
View File

@ -62,6 +62,23 @@ struct HARD_REG_SET
return res;
}
HARD_REG_SET
operator& (const HARD_REG_SET &other) const
{
HARD_REG_SET res;
for (unsigned int i = 0; i < ARRAY_SIZE (elts); ++i)
res.elts[i] = elts[i] & other.elts[i];
return res;
}
HARD_REG_SET &
operator&= (const HARD_REG_SET &other)
{
for (unsigned int i = 0; i < ARRAY_SIZE (elts); ++i)
elts[i] &= other.elts[i];
return *this;
}
HARD_REG_ELT_TYPE elts[HARD_REG_SET_LONGS];
};
typedef const HARD_REG_SET &const_hard_reg_set;
@ -92,10 +109,10 @@ struct hard_reg_set_container
CLEAR_HARD_REG_SET and SET_HARD_REG_SET.
These take just one argument.
Also define macros for combining hard reg sets:
IOR_HARD_REG_SET and AND_HARD_REG_SET.
These take two arguments TO and FROM; they read from FROM
and combine bitwise into TO. Define also two variants
Also define a macro for combining hard reg sets:
IOR_HARD_REG_SET
This takes two arguments TO and FROM; it reads from FROM
and combines bitwise into TO. Define also
IOR_COMPL_HARD_REG_SET and AND_COMPL_HARD_REG_SET
which use the complement of the set FROM.
@ -122,7 +139,6 @@ struct hard_reg_set_container
#define IOR_HARD_REG_SET(TO, FROM) ((TO) |= (FROM))
#define IOR_COMPL_HARD_REG_SET(TO, FROM) ((TO) |= ~ (FROM))
#define AND_HARD_REG_SET(TO, FROM) ((TO) &= (FROM))
#define AND_COMPL_HARD_REG_SET(TO, FROM) ((TO) &= ~ (FROM))
static inline bool
@ -186,13 +202,6 @@ SET_HARD_REG_SET (HARD_REG_SET &set)
set.elts[i] = -1;
}
inline void
AND_HARD_REG_SET (HARD_REG_SET &to, const_hard_reg_set from)
{
for (unsigned int i = 0; i < ARRAY_SIZE (to.elts); ++i)
to.elts[i] &= from.elts[i];
}
inline void
AND_COMPL_HARD_REG_SET (HARD_REG_SET &to, const_hard_reg_set from)
{

6
gcc/ira-color.c
View File

@ -382,8 +382,7 @@ add_allocno_hard_regs_to_forest (allocno_hard_regs_node_t *roots,
hard_regs_node_vec.safe_push (node);
else if (hard_reg_set_intersect_p (hv->set, node->hard_regs->set))
{
temp_set = hv->set;
AND_HARD_REG_SET (temp_set, node->hard_regs->set);
temp_set = hv->set & node->hard_regs->set;
hv2 = add_allocno_hard_regs (temp_set, hv->cost);
add_allocno_hard_regs_to_forest (&node->first, hv2);
}
@ -897,8 +896,7 @@ setup_left_conflict_sizes_p (ira_allocno_t a)
int j, n, hard_regno;
enum reg_class aclass;
temp_set = temp_node->hard_regs->set;
AND_HARD_REG_SET (temp_set, profitable_hard_regs);
temp_set = temp_node->hard_regs->set & profitable_hard_regs;
aclass = ALLOCNO_CLASS (a);
for (n = 0, j = ira_class_hard_regs_num[aclass] - 1; j >= 0; j--)
{

8
gcc/ira-conflicts.c
View File

@ -662,15 +662,13 @@ print_allocno_conflicts (FILE * file, bool reg_p, ira_allocno_t a)
}
conflicting_hard_regs = OBJECT_TOTAL_CONFLICT_HARD_REGS (obj);
AND_COMPL_HARD_REG_SET (conflicting_hard_regs, ira_no_alloc_regs);
AND_HARD_REG_SET (conflicting_hard_regs,
reg_class_contents[ALLOCNO_CLASS (a)]);
conflicting_hard_regs &= reg_class_contents[ALLOCNO_CLASS (a)];
print_hard_reg_set (file, "\n;; total conflict hard regs:",
conflicting_hard_regs);
conflicting_hard_regs = OBJECT_CONFLICT_HARD_REGS (obj);
AND_COMPL_HARD_REG_SET (conflicting_hard_regs, ira_no_alloc_regs);
AND_HARD_REG_SET (conflicting_hard_regs,
reg_class_contents[ALLOCNO_CLASS (a)]);
conflicting_hard_regs &= reg_class_contents[ALLOCNO_CLASS (a)];
print_hard_reg_set (file, ";; conflict hard regs:",
conflicting_hard_regs);
putc ('\n', file);
@ -743,7 +741,7 @@ ira_build_conflicts (void)
{
temp_hard_reg_set = reg_class_contents[base];
AND_COMPL_HARD_REG_SET (temp_hard_reg_set, ira_no_alloc_regs);
AND_HARD_REG_SET (temp_hard_reg_set, call_used_reg_set);
temp_hard_reg_set &= call_used_reg_set;
}
FOR_EACH_ALLOCNO (a, ai)
{

4
gcc/ira-costs.c
View File

@ -254,9 +254,7 @@ restrict_cost_classes (cost_classes_t full, machine_mode mode,
/* Calculate the set of registers in CL that belong to REGS and
are valid for MODE. */
HARD_REG_SET valid_for_cl;
valid_for_cl = reg_class_contents[cl];
AND_HARD_REG_SET (valid_for_cl, regs);
HARD_REG_SET valid_for_cl = reg_class_contents[cl] & regs;
AND_COMPL_HARD_REG_SET (valid_for_cl,
ira_prohibited_class_mode_regs[cl][mode]);
AND_COMPL_HARD_REG_SET (valid_for_cl, ira_no_alloc_regs);

11
gcc/ira.c
View File

@ -757,8 +757,7 @@ setup_stack_reg_pressure_class (void)
for (i = 0; i < ira_pressure_classes_num; i++)
{
cl = ira_pressure_classes[i];
temp_hard_regset2 = temp_hard_regset;
AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]);
temp_hard_regset2 = temp_hard_regset & reg_class_contents[cl];
size = hard_reg_set_size (temp_hard_regset2);
if (best < size)
{
@ -1117,8 +1116,8 @@ setup_class_translate_array (enum reg_class *class_translate,
for (i = 0; i < classes_num; i++)
{
aclass = classes[i];
temp_hard_regset = reg_class_contents[aclass];
AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
temp_hard_regset = (reg_class_contents[aclass]
& reg_class_contents[cl]);
AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs);
if (! hard_reg_set_empty_p (temp_hard_regset))
{
@ -1262,8 +1261,8 @@ setup_reg_class_relations (void)
}
ira_reg_class_subunion[cl1][cl2] = NO_REGS;
ira_reg_class_superunion[cl1][cl2] = NO_REGS;
intersection_set = reg_class_contents[cl1];
AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]);
intersection_set = (reg_class_contents[cl1]
& reg_class_contents[cl2]);
AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs);
union_set = reg_class_contents[cl1];
IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]);

5
gcc/reginfo.c
View File

@ -378,7 +378,7 @@ init_reg_sets_1 (void)
else
CLEAR_REG_SET (fixed_reg_set_regset);
AND_HARD_REG_SET (operand_reg_set, accessible_reg_set);
operand_reg_set &= accessible_reg_set;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
/* As a special exception, registers whose class is NO_REGS are
@ -1317,8 +1317,7 @@ record_subregs_of_mode (rtx subreg, bool partial_def)
}
if (valid_mode_changes[regno])
AND_HARD_REG_SET (*valid_mode_changes[regno],
simplifiable_subregs (shape));
*valid_mode_changes[regno] &= simplifiable_subregs (shape);
else
{
valid_mode_changes[regno]

5
gcc/reload1.c
View File

@ -1399,7 +1399,7 @@ maybe_fix_stack_asms (void)
/* Those of the registers which are clobbered, but allowed by the
constraints, must be usable as reload registers. So clear them
out of the life information. */
AND_HARD_REG_SET (allowed, clobbered);
allowed &= clobbered;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (TEST_HARD_REG_BIT (allowed, i))
{
@ -4310,8 +4310,7 @@ finish_spills (int global)
may be not included in the value calculated here because
of possible removing caller-saves insns (see function
delete_caller_save_insns. */
chain->used_spill_regs = ~used_by_pseudos;
AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
chain->used_spill_regs = ~used_by_pseudos & used_spill_regs;
}
}

2
gcc/resource.c
View File

@ -582,7 +582,7 @@ find_dead_or_set_registers (rtx_insn *target, struct resources *res,
&fallthrough_res, 0, jump_count,
set, needed);
IOR_HARD_REG_SET (fallthrough_res.regs, target_res.regs);
AND_HARD_REG_SET (res->regs, fallthrough_res.regs);
res->regs &= fallthrough_res.regs;
break;
}
else

3
gcc/sel-sched.c
View File

@ -1245,8 +1245,7 @@ mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p,
/* Leave only registers available for this mode. */
if (!sel_hrd.regs_for_mode_ok[mode])
init_regs_for_mode (mode);
AND_HARD_REG_SET (reg_rename_p->available_for_renaming,
sel_hrd.regs_for_mode[mode]);
reg_rename_p->available_for_renaming &= sel_hrd.regs_for_mode[mode];
/* Exclude registers that are partially call clobbered. */
if (def->crosses_call