Michael Meissner
parent
6e5ea9350f
commit
dc4f83ca6a
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@ -3135,7 +3135,7 @@
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(set (match_operand:DF 0 "gpc_reg_operand" "")
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(minus:DF (subreg:DF (match_dup 2) 0)
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(match_dup 5)))]
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"! TARGET_POWERPC64"
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"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
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"
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{
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operands[2] = gen_reg_rtx (DImode);
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@ -3152,7 +3152,7 @@
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(set (match_operand:DF 0 "gpc_reg_operand" "")
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(minus:DF (subreg:DF (match_dup 2) 0)
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(match_dup 4)))]
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"! TARGET_POWERPC64"
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"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
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"
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{
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operands[2] = gen_reg_rtx (DImode);
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@ -4017,8 +4017,9 @@
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(define_insn ""
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[(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
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(match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
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"! TARGET_POWERPC64 && (register_operand (operands[0], DFmode)
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|| register_operand (operands[1], DFmode))"
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"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
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&& (register_operand (operands[0], DFmode)
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|| register_operand (operands[1], DFmode))"
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"*
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{
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switch (which_alternative)
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@ -4056,11 +4057,49 @@
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[(set_attr "type" "*,load,*,*,fp,fpload,*")
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(set_attr "length" "8,8,8,8,*,*,*")])
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(define_insn ""
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[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r")
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(match_operand:DF 1 "input_operand" "r,o,r,G"))]
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"! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
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&& (register_operand (operands[0], DFmode)
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|| register_operand (operands[1], DFmode))"
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"*
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{
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switch (which_alternative)
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{
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case 0:
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/* We normally copy the low-numbered register first. However, if
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the first register operand 0 is the same as the second register of
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operand 1, we must copy in the opposite order. */
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if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
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return \"mr %L0,%L1\;mr %0,%1\";
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else
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return \"mr %0,%1\;mr %L0,%L1\";
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case 1:
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/* If the low-address word is used in the address, we must load it
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last. Otherwise, load it first. Note that we cannot have
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auto-increment in that case since the address register is known to be
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dead. */
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if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
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operands [1], 0))
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return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
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else
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return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
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case 2:
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return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
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case 3:
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return \"#\";
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}
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}"
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[(set_attr "type" "*,load,*,*")
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(set_attr "length" "8,8,8,8")])
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(define_insn ""
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[(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
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(match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
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"TARGET_POWERPC64 && (register_operand (operands[0], DFmode)
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|| register_operand (operands[1], DFmode))"
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"TARGET_POWERPC64 && TARGET_HARD_FLOAT
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&& (register_operand (operands[0], DFmode)
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|| register_operand (operands[1], DFmode))"
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"@
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mr %0,%1
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ld%U1%X1 %0,%1
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@ -4070,6 +4109,19 @@
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lfd%U1%X1 %0,%1
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stfd%U0%X0 %1,%0"
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[(set_attr "type" "*,load,*,*,fp,fpload,*")])
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(define_insn ""
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[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r")
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(match_operand:DF 1 "input_operand" "r,o,r,G"))]
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"TARGET_POWERPC64 && TARGET_SOFT_FLOAT
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&& (register_operand (operands[0], DFmode)
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|| register_operand (operands[1], DFmode))"
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"@
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mr %0,%1
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ld%U1%X1 %0,%1
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sd%U0%X0 %1,%0
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#"
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[(set_attr "type" "*,load,*,*")])
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;; Next come the multi-word integer load and store and the load and store
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;; multiple insns.
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@ -4203,12 +4255,15 @@
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[(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
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(match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
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(clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
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"TARGET_MULTIPLE && ! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
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|| gpc_reg_operand (operands[1], TImode))"
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"TARGET_MULTIPLE && TARGET_POWER && ! TARGET_POWERPC64
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&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
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"*
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{
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switch (which_alternative)
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{
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default:
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abort ();
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case 0:
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return \"{stsi|stswi} %1,%P0,16\";
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@ -4250,6 +4305,51 @@
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[(set_attr "type" "*,load,load,*,*")
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(set_attr "length" "*,16,16,*,16")])
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(define_insn ""
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[(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
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(match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
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(clobber (match_scratch:SI 2 "=X,X,X"))]
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"TARGET_MULTIPLE && !TARGET_POWER && ! TARGET_POWERPC64
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&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
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"*
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{
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switch (which_alternative)
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{
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default:
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abort ();
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case 0:
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return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
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case 1:
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/* Normally copy registers with lowest numbered register copied first.
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But copy in the other order if the first register of the output
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is the second, third, or fourth register in the input. */
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if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
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&& REGNO (operands[0]) <= REGNO (operands[1]) + 3)
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return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
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else
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return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
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case 2:
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/* If the address register is the same as the register for the lowest-
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addressed word, load it last. Similarly for the next two words.
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Otherwise load lowest address to highest. */
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if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
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operands[1], 0))
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return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
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else if (refers_to_regno_p (REGNO (operands[0]) + 1,
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REGNO (operands[0]) + 2, operands[1], 0))
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return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
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else if (refers_to_regno_p (REGNO (operands[0]) + 2,
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REGNO (operands[0]) + 3, operands[1], 0))
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return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
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else
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return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
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}
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}"
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[(set_attr "type" "load,*,*")
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(set_attr "length" "16,16,16")])
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(define_insn ""
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[(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
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(match_operand:TI 1 "input_operand" "r,m,r"))]
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@ -4399,7 +4499,7 @@
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[(set (match_operand:SI 1 "indirect_operand" "=Q")
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(match_operand:SI 2 "gpc_reg_operand" "r"))
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(clobber (match_scratch:SI 3 "=q"))])]
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"TARGET_MULTIPLE && !TARGET_POWERPC"
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"TARGET_MULTIPLE && TARGET_POWER"
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"{stsi|stswi} %2,%P1,%O0")
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(define_insn ""
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@ -4407,7 +4507,7 @@
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[(set (match_operand:SI 1 "indirect_operand" "=Q")
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(match_operand:SI 2 "gpc_reg_operand" "r"))
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(clobber (match_scratch:SI 3 "X"))])]
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"TARGET_MULTIPLE && TARGET_POWERPC"
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"TARGET_MULTIPLE && !TARGET_POWER"
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"{stsi|stswi} %2,%P1,%O0")
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;; Define insns that do load or store with update. Some of these we can
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