[ARM] PR target/68214: Delete IP-reg-clobbering call-through-mem patterns

PR target/68214
	* config/arm/arm.md (*call_mem): Delete pattern.
	(*call_value_mem): Likewise.
	* config/arm/arm.c (output_call_mem): Delete.
	* config/arm/arm-protos.h (output_call_mem): Delete prototype.

From-SVN: r231252
This commit is contained in:
Kyrylo Tkachov 2015-12-04 09:44:42 +00:00 committed by Kyrylo Tkachov
parent d90085b9dc
commit dcc75da435
4 changed files with 8 additions and 70 deletions

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@ -1,3 +1,11 @@
2015-12-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/68214
* config/arm/arm.md (*call_mem): Delete pattern.
(*call_value_mem): Likewise.
* config/arm/arm.c (output_call_mem): Delete.
* config/arm/arm-protos.h (output_call_mem): Delete prototype.
2015-12-04 Bin Cheng <bin.cheng@arm.com>
* config/aarch64/atomics.md (atomic_store<mode>): Use predicate

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@ -132,7 +132,6 @@ extern bool arm_const_double_by_parts (rtx);
extern bool arm_const_double_by_immediates (rtx);
extern void arm_emit_call_insn (rtx, rtx, bool);
extern const char *output_call (rtx *);
extern const char *output_call_mem (rtx *);
void arm_emit_movpair (rtx, rtx);
extern const char *output_mov_long_double_arm_from_arm (rtx *);
extern const char *output_move_double (rtx *, bool, int *count);

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@ -17913,41 +17913,6 @@ output_call (rtx *operands)
return "";
}
/* Output a 'call' insn that is a reference in memory. This is
disabled for ARMv5 and we prefer a blx instead because otherwise
there's a significant performance overhead. */
const char *
output_call_mem (rtx *operands)
{
gcc_assert (!arm_arch5);
if (TARGET_INTERWORK)
{
output_asm_insn ("ldr%?\t%|ip, %0", operands);
output_asm_insn ("mov%?\t%|lr, %|pc", operands);
output_asm_insn ("bx%?\t%|ip", operands);
}
else if (regno_use_in (LR_REGNUM, operands[0]))
{
/* LR is used in the memory address. We load the address in the
first instruction. It's safe to use IP as the target of the
load since the call will kill it anyway. */
output_asm_insn ("ldr%?\t%|ip, %0", operands);
output_asm_insn ("mov%?\t%|lr, %|pc", operands);
if (arm_arch4t)
output_asm_insn ("bx%?\t%|ip", operands);
else
output_asm_insn ("mov%?\t%|pc, %|ip", operands);
}
else
{
output_asm_insn ("mov%?\t%|lr, %|pc", operands);
output_asm_insn ("ldr%?\t%|pc, %0", operands);
}
return "";
}
/* Output a move from arm registers to arm registers of a long double
OPERANDS[0] is the destination.
OPERANDS[1] is the source. */

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@ -7662,23 +7662,6 @@
)
;; Note: not used for armv5+ because the sequence used (ldr pc, ...) is not
;; considered a function call by the branch predictor of some cores (PR40887).
;; Falls back to blx rN (*call_reg_armv5).
(define_insn "*call_mem"
[(call (mem:SI (match_operand:SI 0 "call_memory_operand" "m"))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
(clobber (reg:SI LR_REGNUM))]
"TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)"
"*
return output_call_mem (operands);
"
[(set_attr "length" "12")
(set_attr "type" "call")]
)
(define_expand "call_value"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand 1 "memory_operand" "")
@ -7742,23 +7725,6 @@
(set_attr "type" "call")]
)
;; Note: see *call_mem
(define_insn "*call_value_mem"
[(set (match_operand 0 "" "")
(call (mem:SI (match_operand:SI 1 "call_memory_operand" "m"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
(clobber (reg:SI LR_REGNUM))]
"TARGET_ARM && !arm_arch5 && (!CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
&& !SIBLING_CALL_P (insn)"
"*
return output_call_mem (&operands[1]);
"
[(set_attr "length" "12")
(set_attr "type" "call")]
)
;; Allow calls to SYMBOL_REFs specially as they are not valid general addresses
;; The 'a' causes the operand to be treated as an address, i.e. no '#' output.