[ARM] PR target/68214: Delete IP-reg-clobbering call-through-mem patterns
PR target/68214 * config/arm/arm.md (*call_mem): Delete pattern. (*call_value_mem): Likewise. * config/arm/arm.c (output_call_mem): Delete. * config/arm/arm-protos.h (output_call_mem): Delete prototype. From-SVN: r231252
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@ -1,3 +1,11 @@
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2015-12-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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PR target/68214
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* config/arm/arm.md (*call_mem): Delete pattern.
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(*call_value_mem): Likewise.
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* config/arm/arm.c (output_call_mem): Delete.
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* config/arm/arm-protos.h (output_call_mem): Delete prototype.
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2015-12-04 Bin Cheng <bin.cheng@arm.com>
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* config/aarch64/atomics.md (atomic_store<mode>): Use predicate
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@ -132,7 +132,6 @@ extern bool arm_const_double_by_parts (rtx);
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extern bool arm_const_double_by_immediates (rtx);
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extern void arm_emit_call_insn (rtx, rtx, bool);
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extern const char *output_call (rtx *);
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extern const char *output_call_mem (rtx *);
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void arm_emit_movpair (rtx, rtx);
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extern const char *output_mov_long_double_arm_from_arm (rtx *);
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extern const char *output_move_double (rtx *, bool, int *count);
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@ -17913,41 +17913,6 @@ output_call (rtx *operands)
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return "";
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}
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/* Output a 'call' insn that is a reference in memory. This is
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disabled for ARMv5 and we prefer a blx instead because otherwise
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there's a significant performance overhead. */
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const char *
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output_call_mem (rtx *operands)
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{
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gcc_assert (!arm_arch5);
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if (TARGET_INTERWORK)
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{
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output_asm_insn ("ldr%?\t%|ip, %0", operands);
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output_asm_insn ("mov%?\t%|lr, %|pc", operands);
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output_asm_insn ("bx%?\t%|ip", operands);
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}
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else if (regno_use_in (LR_REGNUM, operands[0]))
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{
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/* LR is used in the memory address. We load the address in the
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first instruction. It's safe to use IP as the target of the
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load since the call will kill it anyway. */
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output_asm_insn ("ldr%?\t%|ip, %0", operands);
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output_asm_insn ("mov%?\t%|lr, %|pc", operands);
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if (arm_arch4t)
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output_asm_insn ("bx%?\t%|ip", operands);
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else
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output_asm_insn ("mov%?\t%|pc, %|ip", operands);
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}
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else
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{
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output_asm_insn ("mov%?\t%|lr, %|pc", operands);
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output_asm_insn ("ldr%?\t%|pc, %0", operands);
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}
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return "";
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}
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/* Output a move from arm registers to arm registers of a long double
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OPERANDS[0] is the destination.
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OPERANDS[1] is the source. */
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@ -7662,23 +7662,6 @@
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)
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;; Note: not used for armv5+ because the sequence used (ldr pc, ...) is not
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;; considered a function call by the branch predictor of some cores (PR40887).
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;; Falls back to blx rN (*call_reg_armv5).
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(define_insn "*call_mem"
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[(call (mem:SI (match_operand:SI 0 "call_memory_operand" "m"))
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(match_operand 1 "" ""))
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(use (match_operand 2 "" ""))
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(clobber (reg:SI LR_REGNUM))]
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"TARGET_ARM && !arm_arch5 && !SIBLING_CALL_P (insn)"
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"*
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return output_call_mem (operands);
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"
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[(set_attr "length" "12")
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(set_attr "type" "call")]
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)
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(define_expand "call_value"
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[(parallel [(set (match_operand 0 "" "")
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(call (match_operand 1 "memory_operand" "")
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@ -7742,23 +7725,6 @@
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(set_attr "type" "call")]
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)
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;; Note: see *call_mem
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(define_insn "*call_value_mem"
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[(set (match_operand 0 "" "")
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(call (mem:SI (match_operand:SI 1 "call_memory_operand" "m"))
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(match_operand 2 "" "")))
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(use (match_operand 3 "" ""))
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(clobber (reg:SI LR_REGNUM))]
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"TARGET_ARM && !arm_arch5 && (!CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
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&& !SIBLING_CALL_P (insn)"
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"*
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return output_call_mem (&operands[1]);
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"
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[(set_attr "length" "12")
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(set_attr "type" "call")]
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)
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;; Allow calls to SYMBOL_REFs specially as they are not valid general addresses
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;; The 'a' causes the operand to be treated as an address, i.e. no '#' output.
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