ia64.h (MASK_INLINE_DIV_LAT): Remove.
* config/ia64/ia64.h (MASK_INLINE_DIV_LAT): Remove. (MASK_INLINE_DIV_THR): Remove. (TARGET_INLINE_DIV_LAT): Remove. (TARGET_INLINE_DIV_THR): Remove. (TARGET_INLINE_DIV): Remove. (MASK_INLINE_FLOAT_DIV_LAT): New macro. (MASK_INLINE_FLOAT_DIV_THR): New macro. (MASK_INLINE_INT_DIV_LAT): New macro. (MASK_INLINE_INT_DIV_THR): New macro. (TARGET_INLINE_FLOAT_DIV_LAT): New macro. (TARGET_INLINE_FLOAT_DIV_THR): New macro. (TARGET_INLINE_INT_DIV_LAT): New macro. (TARGET_INLINE_INT_DIV_THR): New macro. (TARGET_INLINE_FLOAT_DIV): New macro. (TARGET_INLINE_INT_DIV): New macro. * config/ia64/ia64.md (divsi3): Change to use new macros. (modsi3): Ditto. (udivsi3): Ditto. (umodsi3): Ditto. (divsi3_internal): Ditto. (divdi3): Ditto. (moddi3): Ditto. (udivdi3): Ditto. (umoddi3): Ditto. (divdi3_internal_lat): Ditto. (divdi3_internal_thr): Ditto. (divsf3): Ditto. (divsf3_internal_lat): Ditto. (divsf3_internal_thr): Ditto. (divdf3): Ditto. (divdf3_internal_lat): Ditto. (divdf3_internal_thr): Ditto. (divtf3): Ditto. (divtf3_internal_lat): Ditto. (divtf3_internal_thr): Ditto. * config/ia64/ia64.c (ia64_override_options): Change to check new macros for conflicts in settings. * doc/invoke.texi (-minline-divide-min-latency): Remove. (-minline-divide-max-throughput): Remove. (-minline-float-divide-min-latency): New. (-minline-float-divide-max-throughput): New. (-minline-int-divide-min-latency): New. (-minline-int-divide-max-throughput): New. From-SVN: r58727
This commit is contained in:
Steve Ellcey
Steve Ellcey
parent
0e75523eb4
commit
dcffbadece
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@ -1,3 +1,49 @@
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2002-11-01 Steve Ellcey <sje@cup.hp.com>
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* config/ia64/ia64.h (MASK_INLINE_DIV_LAT): Remove.
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(MASK_INLINE_DIV_THR): Remove.
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(TARGET_INLINE_DIV_LAT): Remove.
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(TARGET_INLINE_DIV_THR): Remove.
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(TARGET_INLINE_DIV): Remove.
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(MASK_INLINE_FLOAT_DIV_LAT): New macro.
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(MASK_INLINE_FLOAT_DIV_THR): New macro.
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(MASK_INLINE_INT_DIV_LAT): New macro.
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(MASK_INLINE_INT_DIV_THR): New macro.
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(TARGET_INLINE_FLOAT_DIV_LAT): New macro.
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(TARGET_INLINE_FLOAT_DIV_THR): New macro.
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(TARGET_INLINE_INT_DIV_LAT): New macro.
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(TARGET_INLINE_INT_DIV_THR): New macro.
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(TARGET_INLINE_FLOAT_DIV): New macro.
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(TARGET_INLINE_INT_DIV): New macro.
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* config/ia64/ia64.md (divsi3): Change to use new macros.
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(modsi3): Ditto.
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(udivsi3): Ditto.
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(umodsi3): Ditto.
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(divsi3_internal): Ditto.
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(divdi3): Ditto.
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(moddi3): Ditto.
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(udivdi3): Ditto.
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(umoddi3): Ditto.
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(divdi3_internal_lat): Ditto.
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(divdi3_internal_thr): Ditto.
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(divsf3): Ditto.
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(divsf3_internal_lat): Ditto.
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(divsf3_internal_thr): Ditto.
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(divdf3): Ditto.
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(divdf3_internal_lat): Ditto.
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(divdf3_internal_thr): Ditto.
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(divtf3): Ditto.
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(divtf3_internal_lat): Ditto.
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(divtf3_internal_thr): Ditto.
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* config/ia64/ia64.c (ia64_override_options): Change
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to check new macros for conflicts in settings.
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* doc/invoke.texi (-minline-divide-min-latency): Remove.
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(-minline-divide-max-throughput): Remove.
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(-minline-float-divide-min-latency): New.
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(-minline-float-divide-max-throughput): New.
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(-minline-int-divide-min-latency): New.
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(-minline-int-divide-max-throughput): New.
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2002-11-01 Richard Earnshaw (rearnsha@arm.com)
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PR target/7856
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@ -4169,10 +4169,16 @@ ia64_override_options ()
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if (TARGET_AUTO_PIC)
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target_flags |= MASK_CONST_GP;
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if (TARGET_INLINE_DIV_LAT && TARGET_INLINE_DIV_THR)
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if (TARGET_INLINE_FLOAT_DIV_LAT && TARGET_INLINE_FLOAT_DIV_THR)
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{
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warning ("cannot optimize division for both latency and throughput");
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target_flags &= ~MASK_INLINE_DIV_THR;
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warning ("cannot optimize floating point division for both latency and throughput");
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target_flags &= ~MASK_INLINE_FLOAT_DIV_THR;
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}
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if (TARGET_INLINE_INT_DIV_LAT && TARGET_INLINE_INT_DIV_THR)
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{
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warning ("cannot optimize integer division for both latency and throughput");
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target_flags &= ~MASK_INLINE_INT_DIV_THR;
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}
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if (ia64_fixed_range_string)
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@ -85,9 +85,13 @@ extern int target_flags;
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#define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */
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#define MASK_INLINE_DIV_LAT 0x00000800 /* inline div, min latency. */
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#define MASK_INLINE_FLOAT_DIV_LAT 0x00000800 /* inline div, min latency. */
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#define MASK_INLINE_DIV_THR 0x00001000 /* inline div, max throughput. */
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#define MASK_INLINE_FLOAT_DIV_THR 0x00001000 /* inline div, max throughput. */
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#define MASK_INLINE_INT_DIV_LAT 0x00000800 /* inline div, min latency. */
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#define MASK_INLINE_INT_DIV_THR 0x00001000 /* inline div, max throughput. */
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#define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
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@ -113,12 +117,19 @@ extern int target_flags;
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#define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC)
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#define TARGET_INLINE_DIV_LAT (target_flags & MASK_INLINE_DIV_LAT)
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#define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT)
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#define TARGET_INLINE_DIV_THR (target_flags & MASK_INLINE_DIV_THR)
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#define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR)
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#define TARGET_INLINE_DIV \
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(target_flags & (MASK_INLINE_DIV_LAT | MASK_INLINE_DIV_THR))
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#define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT)
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#define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR)
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#define TARGET_INLINE_FLOAT_DIV \
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(target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR))
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#define TARGET_INLINE_INT_DIV \
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(target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR))
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#define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM)
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@ -165,10 +176,14 @@ extern int ia64_tls_size;
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N_("gp is constant (but save/restore gp on indirect calls)") }, \
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{ "auto-pic", MASK_AUTO_PIC, \
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N_("Generate self-relocatable code") }, \
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{ "inline-divide-min-latency", MASK_INLINE_DIV_LAT, \
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N_("Generate inline division, optimize for latency") }, \
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{ "inline-divide-max-throughput", MASK_INLINE_DIV_THR, \
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N_("Generate inline division, optimize for throughput") }, \
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{ "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \
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N_("Generate inline floating point division, optimize for latency") },\
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{ "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \
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N_("Generate inline floating point division, optimize for throughput") },\
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{ "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \
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N_("Generate inline integer division, optimize for latency") }, \
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{ "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \
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N_("Generate inline integer division, optimize for throughput") },\
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{ "dwarf2-asm", MASK_DWARF2_ASM, \
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N_("Enable Dwarf 2 line debug info via GNU as")}, \
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{ "no-dwarf2-asm", -MASK_DWARF2_ASM, \
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@ -1987,7 +1987,7 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(div:SI (match_operand:SI 1 "general_operand" "")
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(match_operand:SI 2 "general_operand" "")))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
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{
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rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
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REAL_VALUE_TYPE twon34_r;
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@ -2021,7 +2021,7 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(mod:SI (match_operand:SI 1 "general_operand" "")
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(match_operand:SI 2 "general_operand" "")))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
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{
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rtx op2_neg, op1_di, div;
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@ -2044,7 +2044,7 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(udiv:SI (match_operand:SI 1 "general_operand" "")
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(match_operand:SI 2 "general_operand" "")))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
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{
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rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
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REAL_VALUE_TYPE twon34_r;
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@ -2078,7 +2078,7 @@
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[(set (match_operand:SI 0 "register_operand" "")
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(umod:SI (match_operand:SI 1 "general_operand" "")
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(match_operand:SI 2 "general_operand" "")))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
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{
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rtx op2_neg, op1_di, div;
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@ -2105,7 +2105,7 @@
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(clobber (match_scratch:TF 5 "=&f"))
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(clobber (match_scratch:BI 6 "=c"))
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(use (match_operand:TF 3 "fr_register_operand" "f"))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
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"#"
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"&& reload_completed"
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[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
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@ -2375,7 +2375,7 @@
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[(set (match_operand:DI 0 "register_operand" "")
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(div:DI (match_operand:DI 1 "general_operand" "")
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(match_operand:DI 2 "general_operand" "")))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
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{
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rtx op1_tf, op2_tf, op0_tf;
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@ -2391,7 +2391,7 @@
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op2_tf = gen_reg_rtx (TFmode);
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expand_float (op2_tf, operands[2], 0);
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if (TARGET_INLINE_DIV_LAT)
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if (TARGET_INLINE_INT_DIV_LAT)
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emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
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else
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emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
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@ -2404,7 +2404,7 @@
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[(set (match_operand:DI 0 "register_operand" "")
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(mod:SI (match_operand:DI 1 "general_operand" "")
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(match_operand:DI 2 "general_operand" "")))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
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{
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rtx op2_neg, div;
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@ -2421,7 +2421,7 @@
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[(set (match_operand:DI 0 "register_operand" "")
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(udiv:DI (match_operand:DI 1 "general_operand" "")
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(match_operand:DI 2 "general_operand" "")))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
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{
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rtx op1_tf, op2_tf, op0_tf;
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@ -2437,7 +2437,7 @@
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op2_tf = gen_reg_rtx (TFmode);
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expand_float (op2_tf, operands[2], 1);
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if (TARGET_INLINE_DIV_LAT)
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if (TARGET_INLINE_INT_DIV_LAT)
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emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
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else
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emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
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@ -2450,7 +2450,7 @@
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[(set (match_operand:DI 0 "register_operand" "")
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(umod:DI (match_operand:DI 1 "general_operand" "")
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(match_operand:DI 2 "general_operand" "")))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
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{
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rtx op2_neg, div;
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@ -2471,7 +2471,7 @@
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(clobber (match_scratch:TF 4 "=&f"))
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(clobber (match_scratch:TF 5 "=&f"))
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(clobber (match_scratch:BI 6 "=c"))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_LAT"
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"#"
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"&& reload_completed"
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[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
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@ -2530,7 +2530,7 @@
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(clobber (match_scratch:TF 3 "=&f"))
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(clobber (match_scratch:TF 4 "=f"))
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(clobber (match_scratch:BI 5 "=c"))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_THR"
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"#"
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"&& reload_completed"
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[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
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@ -2681,10 +2681,10 @@
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[(set (match_operand:SF 0 "fr_register_operand" "")
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(div:SF (match_operand:SF 1 "fr_register_operand" "")
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(match_operand:SF 2 "fr_register_operand" "")))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
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{
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rtx insn;
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if (TARGET_INLINE_DIV_LAT)
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if (TARGET_INLINE_FLOAT_DIV_LAT)
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insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
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else
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insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
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@ -2699,7 +2699,7 @@
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(clobber (match_scratch:TF 3 "=&f"))
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(clobber (match_scratch:TF 4 "=f"))
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(clobber (match_scratch:BI 5 "=c"))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
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"#"
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"&& reload_completed"
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[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
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@ -2756,7 +2756,7 @@
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(clobber (match_scratch:TF 3 "=&f"))
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(clobber (match_scratch:TF 4 "=f"))
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(clobber (match_scratch:BI 5 "=c"))]
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
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"#"
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"&& reload_completed"
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[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
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|
|
@ -2990,10 +2990,10 @@
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[(set (match_operand:DF 0 "fr_register_operand" "")
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(div:DF (match_operand:DF 1 "fr_register_operand" "")
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(match_operand:DF 2 "fr_register_operand" "")))]
|
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
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{
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rtx insn;
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if (TARGET_INLINE_DIV_LAT)
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if (TARGET_INLINE_FLOAT_DIV_LAT)
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insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
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else
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insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
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|
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@ -3009,7 +3009,7 @@
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(clobber (match_scratch:TF 4 "=&f"))
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(clobber (match_scratch:TF 5 "=&f"))
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(clobber (match_scratch:BI 6 "=c"))]
|
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
|
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"#"
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"&& reload_completed"
|
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[(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
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|
|
@ -3089,7 +3089,7 @@
|
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(clobber (match_scratch:TF 3 "=&f"))
|
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(clobber (match_scratch:DF 4 "=f"))
|
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(clobber (match_scratch:BI 5 "=c"))]
|
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
|
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"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
|
||||
|
|
@ -3467,10 +3467,10 @@
|
|||
[(set (match_operand:TF 0 "fr_register_operand" "")
|
||||
(div:TF (match_operand:TF 1 "fr_register_operand" "")
|
||||
(match_operand:TF 2 "fr_register_operand" "")))]
|
||||
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
|
||||
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
|
||||
{
|
||||
rtx insn;
|
||||
if (TARGET_INLINE_DIV_LAT)
|
||||
if (TARGET_INLINE_FLOAT_DIV_LAT)
|
||||
insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]);
|
||||
else
|
||||
insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
|
||||
|
|
@ -3487,7 +3487,7 @@
|
|||
(clobber (match_scratch:TF 5 "=&f"))
|
||||
(clobber (match_scratch:TF 6 "=&f"))
|
||||
(clobber (match_scratch:BI 7 "=c"))]
|
||||
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
|
||||
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
|
||||
|
|
@ -3565,7 +3565,7 @@
|
|||
(clobber (match_scratch:TF 3 "=&f"))
|
||||
(clobber (match_scratch:TF 4 "=&f"))
|
||||
(clobber (match_scratch:BI 5 "=c"))]
|
||||
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
|
||||
"INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
|
||||
"#"
|
||||
"&& reload_completed"
|
||||
[(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
|
||||
|
|
|
|||
|
|
@ -622,8 +622,9 @@ in the following sections.
|
|||
@gccoptlist{
|
||||
-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol
|
||||
-mvolatile-asm-stop -mb-step -mregister-names -mno-sdata @gol
|
||||
-mconstant-gp -mauto-pic -minline-divide-min-latency @gol
|
||||
-minline-divide-max-throughput -mno-dwarf2-asm @gol
|
||||
-mconstant-gp -mauto-pic -minline-float-divide-min-latency @gol
|
||||
-minline-float-divide-max-throughput -minline-int-divide-min-latency @gol
|
||||
-minline-int-divide-max-throughput -mno-dwarf2-asm @gol
|
||||
-mfixed-range=@var{register-range}}
|
||||
|
||||
@emph{D30V Options}
|
||||
|
|
@ -9389,13 +9390,25 @@ useful when compiling kernel code.
|
|||
Generate code that is self-relocatable. This implies @option{-mconstant-gp}.
|
||||
This is useful when compiling firmware code.
|
||||
|
||||
@item -minline-divide-min-latency
|
||||
@opindex minline-divide-min-latency
|
||||
Generate code for inline divides using the minimum latency algorithm.
|
||||
@item -minline-float-divide-min-latency
|
||||
@opindex minline-float-divide-min-latency
|
||||
Generate code for inline divides of floating point values
|
||||
using the minimum latency algorithm.
|
||||
|
||||
@item -minline-divide-max-throughput
|
||||
@opindex minline-divide-max-throughput
|
||||
Generate code for inline divides using the maximum throughput algorithm.
|
||||
@item -minline-float-divide-max-throughput
|
||||
@opindex minline-float-divide-max-throughput
|
||||
Generate code for inline divides of floating point values
|
||||
using the maximum throughput algorithm.
|
||||
|
||||
@item -minline-int-divide-min-latency
|
||||
@opindex minline-int-divide-min-latency
|
||||
Generate code for inline divides of integer values
|
||||
using the minimum latency algorithm.
|
||||
|
||||
@item -minline-int-divide-max-throughput
|
||||
@opindex minline-int-divide-max-throughput
|
||||
Generate code for inline divides of integer values
|
||||
using the maximum throughput algorithm.
|
||||
|
||||
@item -mno-dwarf2-asm
|
||||
@itemx -mdwarf2-asm
|
||||
|
|
|
|||
Loading…
Reference in New Issue