ii386: Add missing two element 64bit vector permutations [PR89021]
In addition to V8QI permutations, several other missing permutations are added for 64bit vector modes for TARGET_SSSE3 and TARGET_SSE4_1 targets. 2021-06-16 Uroš Bizjak <ubizjak@gmail.com> gcc/ PR target/89021 * config/i386/i386-expand.c (expand_vec_perm_2perm_pblendv): Handle 64bit modes for TARGET_SSE4_1. (expand_vec_perm_pshufb2): Handle 64bit modes for TARGET_SSSE3. (expand_vec_perm_even_odd_pack): Handle V4HI mode. (expand_vec_perm_even_odd_1) <case E_V4HImode>: Expand via expand_vec_perm_pshufb2 for TARGET_SSSE3 and via expand_vec_perm_even_odd_pack for TARGET_SSE4_1. * config/i386/mmx.md (mmx_packusdw): New insn pattern.
This commit is contained in:
Uros Bizjak
parent
c25e3bf879
commit
dd835ec24b
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@ -17633,8 +17633,10 @@ expand_vec_perm_pshufb (struct expand_vec_perm_d *d)
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if (vmode == V8QImode)
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{
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rtx m128 = GEN_INT (-128);
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for (i = nelt; i < 16; ++i)
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rperm[i] = constm1_rtx;
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rperm[i] = m128;
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vpmode = V16QImode;
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}
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@ -18972,7 +18974,8 @@ expand_vec_perm_2perm_pblendv (struct expand_vec_perm_d *d, bool two_insn)
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;
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else if (TARGET_AVX && (vmode == V4DFmode || vmode == V8SFmode))
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;
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else if (TARGET_SSE4_1 && GET_MODE_SIZE (vmode) == 16)
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else if (TARGET_SSE4_1 && (GET_MODE_SIZE (vmode) == 16
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|| GET_MODE_SIZE (vmode) == 8))
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;
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else
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return false;
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@ -19229,14 +19232,31 @@ expand_vec_perm_pshufb2 (struct expand_vec_perm_d *d)
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{
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rtx rperm[2][16], vperm, l, h, op, m128;
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unsigned int i, nelt, eltsz;
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machine_mode mode;
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rtx (*gen) (rtx, rtx, rtx);
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if (!TARGET_SSSE3 || GET_MODE_SIZE (d->vmode) != 16)
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if (!TARGET_SSSE3 || (GET_MODE_SIZE (d->vmode) != 16
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&& GET_MODE_SIZE (d->vmode) != 8))
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return false;
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gcc_assert (!d->one_operand_p);
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if (d->testing_p)
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return true;
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switch (GET_MODE_SIZE (d->vmode))
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{
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case 8:
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mode = V8QImode;
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gen = gen_mmx_pshufbv8qi3;
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break;
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case 16:
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mode = V16QImode;
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gen = gen_ssse3_pshufbv16qi3;
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break;
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default:
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gcc_unreachable ();
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}
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nelt = d->nelt;
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eltsz = GET_MODE_UNIT_SIZE (d->vmode);
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@ -19247,7 +19267,7 @@ expand_vec_perm_pshufb2 (struct expand_vec_perm_d *d)
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m128 = GEN_INT (-128);
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for (i = 0; i < nelt; ++i)
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{
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unsigned j, e = d->perm[i];
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unsigned j, k, e = d->perm[i];
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unsigned which = (e >= nelt);
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if (e >= nelt)
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e -= nelt;
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@ -19257,26 +19277,29 @@ expand_vec_perm_pshufb2 (struct expand_vec_perm_d *d)
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rperm[which][i*eltsz + j] = GEN_INT (e*eltsz + j);
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rperm[1-which][i*eltsz + j] = m128;
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}
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for (k = i*eltsz + j; k < 16; ++k)
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rperm[0][k] = rperm[1][k] = m128;
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}
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vperm = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, rperm[0]));
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vperm = force_reg (V16QImode, vperm);
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l = gen_reg_rtx (V16QImode);
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op = gen_lowpart (V16QImode, d->op0);
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emit_insn (gen_ssse3_pshufbv16qi3 (l, op, vperm));
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l = gen_reg_rtx (mode);
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op = gen_lowpart (mode, d->op0);
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emit_insn (gen (l, op, vperm));
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vperm = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, rperm[1]));
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vperm = force_reg (V16QImode, vperm);
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h = gen_reg_rtx (V16QImode);
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op = gen_lowpart (V16QImode, d->op1);
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emit_insn (gen_ssse3_pshufbv16qi3 (h, op, vperm));
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h = gen_reg_rtx (mode);
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op = gen_lowpart (mode, d->op1);
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emit_insn (gen (h, op, vperm));
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op = d->target;
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if (d->vmode != V16QImode)
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op = gen_reg_rtx (V16QImode);
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emit_insn (gen_iorv16qi3 (op, l, h));
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if (d->vmode != mode)
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op = gen_reg_rtx (mode);
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emit_insn (gen_rtx_SET (op, gen_rtx_IOR (mode, l, h)));
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if (op != d->target)
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emit_move_insn (d->target, gen_lowpart (d->vmode, op));
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@ -19455,6 +19478,17 @@ expand_vec_perm_even_odd_pack (struct expand_vec_perm_d *d)
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switch (d->vmode)
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{
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case E_V4HImode:
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/* Required for "pack". */
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if (!TARGET_SSE4_1)
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return false;
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c = 0xffff;
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s = 16;
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half_mode = V2SImode;
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gen_and = gen_andv2si3;
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gen_pack = gen_mmx_packusdw;
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gen_shift = gen_lshrv2si3;
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break;
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case E_V8HImode:
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/* Required for "pack". */
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if (!TARGET_SSE4_1)
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@ -19507,7 +19541,7 @@ expand_vec_perm_even_odd_pack (struct expand_vec_perm_d *d)
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end_perm = true;
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break;
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default:
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/* Only V8QI, V8HI, V16QI, V16HI and V32QI modes
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/* Only V4HI, V8QI, V8HI, V16QI, V16HI and V32QI modes
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are more profitable than general shuffles. */
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return false;
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}
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@ -19698,18 +19732,25 @@ expand_vec_perm_even_odd_1 (struct expand_vec_perm_d *d, unsigned odd)
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break;
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case E_V4HImode:
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if (d->testing_p)
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break;
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/* We need 2*log2(N)-1 operations to achieve odd/even
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with interleave. */
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t1 = gen_reg_rtx (V4HImode);
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emit_insn (gen_mmx_punpckhwd (t1, d->op0, d->op1));
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emit_insn (gen_mmx_punpcklwd (d->target, d->op0, d->op1));
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if (odd)
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t2 = gen_mmx_punpckhwd (d->target, d->target, t1);
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if (TARGET_SSE4_1)
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return expand_vec_perm_even_odd_pack (d);
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else if (TARGET_SSSE3 && !TARGET_SLOW_PSHUFB)
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return expand_vec_perm_pshufb2 (d);
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else
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t2 = gen_mmx_punpcklwd (d->target, d->target, t1);
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emit_insn (t2);
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{
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if (d->testing_p)
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break;
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/* We need 2*log2(N)-1 operations to achieve odd/even
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with interleave. */
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t1 = gen_reg_rtx (V4HImode);
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emit_insn (gen_mmx_punpckhwd (t1, d->op0, d->op1));
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emit_insn (gen_mmx_punpcklwd (d->target, d->op0, d->op1));
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if (odd)
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t2 = gen_mmx_punpckhwd (d->target, d->target, t1);
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else
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t2 = gen_mmx_punpcklwd (d->target, d->target, t1);
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emit_insn (t2);
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}
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break;
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case E_V8HImode:
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@ -2477,6 +2477,22 @@
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(set_attr "type" "mmxshft,sselog,sselog")
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(set_attr "mode" "DI,TI,TI")])
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(define_insn_and_split "mmx_packusdw"
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[(set (match_operand:V4HI 0 "register_operand" "=Yr,*x,Yw")
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(vec_concat:V4HI
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(us_truncate:V2HI
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(match_operand:V2SI 1 "register_operand" "0,0,Yw"))
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(us_truncate:V2HI
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(match_operand:V2SI 2 "register_operand" "Yr,*x,Yw"))))]
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"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
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"#"
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"&& reload_completed"
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[(const_int 0)]
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"ix86_split_mmx_pack (operands, US_TRUNCATE); DONE;"
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[(set_attr "isa" "noavx,noavx,avx")
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(set_attr "type" "sselog")
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(set_attr "mode" "TI")])
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(define_insn_and_split "mmx_punpckhbw"
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[(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
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(vec_select:V8QI
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