Index...
Index: gcc/config/rs6000/emmintrin.h =================================================================== --- gcc/config/rs6000/emmintrin.h (revision 265318) +++ gcc/config/rs6000/emmintrin.h (working copy) @@ -85,7 +85,7 @@ typedef double __m128d __attribute__ ((__vector_si typedef long long __m128i_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1))); typedef double __m128d_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1))); -/* Define two value permute mask */ +/* Define two value permute mask. */ #define _MM_SHUFFLE2(x,y) (((x) << 1) | (y)) /* Create a vector with element 0 as F and the rest zero. */ @@ -201,7 +201,7 @@ _mm_store_pd (double *__P, __m128d __A) extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_storeu_pd (double *__P, __m128d __A) { - *(__m128d *)__P = __A; + *(__m128d_u *)__P = __A; } /* Stores the lower DPFP value. */ @@ -2175,7 +2175,7 @@ _mm_maskmoveu_si128 (__m128i __A, __m128i __B, cha { __v2du hibit = { 0x7f7f7f7f7f7f7f7fUL, 0x7f7f7f7f7f7f7f7fUL}; __v16qu mask, tmp; - __m128i *p = (__m128i*)__C; + __m128i_u *p = (__m128i_u*)__C; tmp = (__v16qu)_mm_loadu_si128(p); mask = (__v16qu)vec_cmpgt ((__v16qu)__B, (__v16qu)hibit); Index: gcc/config/rs6000/xmmintrin.h =================================================================== --- gcc/config/rs6000/xmmintrin.h (revision 265318) +++ gcc/config/rs6000/xmmintrin.h (working copy) @@ -85,6 +85,10 @@ vector types, and their scalar components. */ typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__)); +/* Unaligned version of the same type. */ +typedef float __m128_u __attribute__ ((__vector_size__ (16), __may_alias__, + __aligned__ (1))); + /* Internal data types for implementing the intrinsics. */ typedef float __v4sf __attribute__ ((__vector_size__ (16))); @@ -172,7 +176,7 @@ _mm_store_ps (float *__P, __m128 __A) extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _mm_storeu_ps (float *__P, __m128 __A) { - *(__m128 *)__P = __A; + *(__m128_u *)__P = __A; } /* Store four SPFP values in reverse order. The address must be aligned. */ From-SVN: r265389
This commit is contained in:
parent
d78bcb133d
commit
ddec5aea56
|
@ -85,7 +85,7 @@ typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__));
|
|||
typedef long long __m128i_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1)));
|
||||
typedef double __m128d_u __attribute__ ((__vector_size__ (16), __may_alias__, __aligned__ (1)));
|
||||
|
||||
/* Define two value permute mask */
|
||||
/* Define two value permute mask. */
|
||||
#define _MM_SHUFFLE2(x,y) (((x) << 1) | (y))
|
||||
|
||||
/* Create a vector with element 0 as F and the rest zero. */
|
||||
|
@ -201,7 +201,7 @@ _mm_store_pd (double *__P, __m128d __A)
|
|||
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_mm_storeu_pd (double *__P, __m128d __A)
|
||||
{
|
||||
*(__m128d *)__P = __A;
|
||||
*(__m128d_u *)__P = __A;
|
||||
}
|
||||
|
||||
/* Stores the lower DPFP value. */
|
||||
|
@ -2177,7 +2177,7 @@ _mm_maskmoveu_si128 (__m128i __A, __m128i __B, char *__C)
|
|||
{
|
||||
__v2du hibit = { 0x7f7f7f7f7f7f7f7fUL, 0x7f7f7f7f7f7f7f7fUL};
|
||||
__v16qu mask, tmp;
|
||||
__m128i *p = (__m128i*)__C;
|
||||
__m128i_u *p = (__m128i_u*)__C;
|
||||
|
||||
tmp = (__v16qu)_mm_loadu_si128(p);
|
||||
mask = (__v16qu)vec_cmpgt ((__v16qu)__B, (__v16qu)hibit);
|
||||
|
|
|
@ -85,6 +85,10 @@
|
|||
vector types, and their scalar components. */
|
||||
typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
|
||||
|
||||
/* Unaligned version of the same type. */
|
||||
typedef float __m128_u __attribute__ ((__vector_size__ (16), __may_alias__,
|
||||
__aligned__ (1)));
|
||||
|
||||
/* Internal data types for implementing the intrinsics. */
|
||||
typedef float __v4sf __attribute__ ((__vector_size__ (16)));
|
||||
|
||||
|
@ -172,7 +176,7 @@ _mm_store_ps (float *__P, __m128 __A)
|
|||
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
|
||||
_mm_storeu_ps (float *__P, __m128 __A)
|
||||
{
|
||||
*(__m128 *)__P = __A;
|
||||
*(__m128_u *)__P = __A;
|
||||
}
|
||||
|
||||
/* Store four SPFP values in reverse order. The address must be aligned. */
|
||||
|
|
Loading…
Reference in New Issue