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Fix 31018 -- move TARGET_xxx in i386.md to tuning options 

From-SVN: r122933
This commit is contained in:
Michael Meissner 2007-03-14 22:36:22 +00:00
parent d33d6db009
commit ddff69b972
3 changed files with 62 additions and 19 deletions
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29
gcc/config/i386/i386.c
View File

@ -1192,7 +1192,34 @@ unsigned int ix86_tune_features[X86_TUNE_LAST] = {
m_ATHLON_K8_AMDFAM10 | m_CORE2 | m_GENERIC,
/* X86_TUNE_EXT_80387_CONSTANTS */
m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
/* X86_TUNE_SHORTEN_X87_SSE */
~m_K8,
/* X86_TUNE_AVOID_VECTOR_DECODE */
m_K8 | m_GENERIC64,
/* X86_TUNE_SLOW_IMUL_IMM32_MEM (imul of 32-bit constant and memory is vector
path on AMD machines) */
m_K8 | m_GENERIC64 | m_AMDFAM10,
/* X86_TUNE_SLOW_IMUL_IMM8 (imul of 8-bit constant is vector path on AMD
machines) */
m_K8 | m_GENERIC64 | m_AMDFAM10,
/* X86_TUNE_MOVE_M1_VIA_OR (on pentiums, it is faster to load -1 via OR than
a MOV) */
m_PENT,
/* X86_TUNE_NOT_UNPAIRABLE (NOT is not pairable on Pentium, while XOR is, but
one byte longer). */
m_PENT,
/* X86_TUNE_NOT_VECTORMODE (On AMD K6, NOT is vector decoded with memory
operand that cannot be represented using a modRM byte. The XOR
replacement is long decoded, so this split helps here as well). */
m_K6,
};
/* Feature tests against the various architecture variations. */

16
gcc/config/i386/i386.h
View File

@ -233,6 +233,13 @@ enum ix86_tune_indices {
X86_TUNE_USE_INCDEC,
X86_TUNE_PAD_RETURNS,
X86_TUNE_EXT_80387_CONSTANTS,
X86_TUNE_SHORTEN_X87_SSE,
X86_TUNE_AVOID_VECTOR_DECODE,
X86_TUNE_SLOW_IMUL_IMM32_MEM,
X86_TUNE_SLOW_IMUL_IMM8,
X86_TUNE_MOVE_M1_VIA_OR,
X86_TUNE_NOT_UNPAIRABLE,
X86_TUNE_NOT_VECTORMODE,
X86_TUNE_LAST
};
@ -302,6 +309,15 @@ extern unsigned int ix86_tune_features[X86_TUNE_LAST];
#define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS]
#define TARGET_EXT_80387_CONSTANTS \
ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]
#define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]
#define TARGET_AVOID_VECTOR_DECODE \
ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]
#define TARGET_SLOW_IMUL_IMM32_MEM \
ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]
#define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]
#define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]
#define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]
#define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE]
/* Feature tests against the various architecture variations. */
enum ix86_arch_indices {

36
gcc/config/i386/i386.md
View File

@ -1182,7 +1182,7 @@
(clobber (reg:CC FLAGS_REG))]
"reload_completed
&& operands[1] == constm1_rtx
&& (TARGET_PENTIUM || optimize_size)"
&& (TARGET_MOVE_M1_VIA_OR || optimize_size)"
{
operands[1] = constm1_rtx;
return "or{l}\t{%1, %0|%0, %1}";
@ -1974,7 +1974,7 @@
[(set (match_operand:DI 0 "register_operand" "=r")
(match_operand:DI 1 "const_int_operand" "i"))
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
"TARGET_64BIT && (TARGET_MOVE_M1_VIA_OR || optimize_size)
&& reload_completed
&& operands[1] == constm1_rtx"
{
@ -4433,7 +4433,7 @@
(match_operand:SSEMODEF 1 "memory_operand" ""))
(set (match_operand:SSEMODEI24 2 "register_operand" "")
(fix:SSEMODEI24 (match_dup 0)))]
"!TARGET_K8
"TARGET_SHORTEN_X87_SSE
&& peep2_reg_dead_p (2, operands[0])"
[(set (match_dup 2) (fix:SSEMODEI24 (match_dup 1)))]
"")
@ -4443,7 +4443,7 @@
[(match_scratch:DF 2 "Y2")
(set (match_operand:SSEMODEI24 0 "register_operand" "")
(fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
"(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
"TARGET_AVOID_VECTOR_DECODE && !optimize_size"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
"")
@ -4452,7 +4452,7 @@
[(match_scratch:SF 2 "x")
(set (match_operand:SSEMODEI24 0 "register_operand" "")
(fix:SSEMODEI24 (match_operand:SF 1 "memory_operand" "")))]
"(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
"TARGET_AVOID_VECTOR_DECODE && !optimize_size"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
"")
@ -20024,10 +20024,10 @@
(not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
"!optimize_size
&& peep2_regno_dead_p (0, FLAGS_REG)
&& ((TARGET_PENTIUM
&& ((TARGET_NOT_UNPAIRABLE
&& (!MEM_P (operands[0])
|| !memory_displacement_operand (operands[0], SImode)))
|| (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
|| (TARGET_NOT_VECTORMODE && long_memory_operand (operands[0], SImode)))"
[(parallel [(set (match_dup 0)
(xor:SI (match_dup 1) (const_int -1)))
(clobber (reg:CC FLAGS_REG))])]
@ -20038,10 +20038,10 @@
(not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
"!optimize_size
&& peep2_regno_dead_p (0, FLAGS_REG)
&& ((TARGET_PENTIUM
&& ((TARGET_NOT_UNPAIRABLE
&& (!MEM_P (operands[0])
|| !memory_displacement_operand (operands[0], HImode)))
|| (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
|| (TARGET_NOT_VECTORMODE && long_memory_operand (operands[0], HImode)))"
[(parallel [(set (match_dup 0)
(xor:HI (match_dup 1) (const_int -1)))
(clobber (reg:CC FLAGS_REG))])]
@ -20052,10 +20052,10 @@
(not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
"!optimize_size
&& peep2_regno_dead_p (0, FLAGS_REG)
&& ((TARGET_PENTIUM
&& ((TARGET_NOT_UNPAIRABLE
&& (!MEM_P (operands[0])
|| !memory_displacement_operand (operands[0], QImode)))
|| (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
|| (TARGET_NOT_VECTORMODE && long_memory_operand (operands[0], QImode)))"
[(parallel [(set (match_dup 0)
(xor:QI (match_dup 1) (const_int -1)))
(clobber (reg:CC FLAGS_REG))])]
@ -20237,7 +20237,7 @@
"(GET_MODE (operands[0]) == HImode
|| GET_MODE (operands[0]) == SImode
|| (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
&& (optimize_size || TARGET_PENTIUM)
&& (optimize_size || TARGET_MOVE_M1_VIA_OR)
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (const_int -1))
(clobber (reg:CC FLAGS_REG))])]
@ -20641,7 +20641,7 @@
(mult:DI (match_operand:DI 1 "memory_operand" "")
(match_operand:DI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
"(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
"TARGET_SLOW_IMUL_IMM32_MEM && !optimize_size
&& !satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
@ -20654,7 +20654,7 @@
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])]
"(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
"TARGET_SLOW_IMUL_IMM32_MEM && !optimize_size
&& !satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
@ -20668,7 +20668,7 @@
(mult:SI (match_operand:SI 1 "memory_operand" "")
(match_operand:SI 2 "immediate_operand" ""))))
(clobber (reg:CC FLAGS_REG))])]
"(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
"TARGET_SLOW_IMUL_IMM32_MEM && !optimize_size
&& !satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 1))
(parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
@ -20685,7 +20685,7 @@
(match_operand:DI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:DI 3 "r")]
"(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
"TARGET_SLOW_IMUL_IMM8 && !optimize_size
&& satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
@ -20701,7 +20701,7 @@
(match_operand:SI 2 "const_int_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:SI 3 "r")]
"(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
"TARGET_SLOW_IMUL_IMM8 && !optimize_size
&& satisfies_constraint_K (operands[2])"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
@ -20717,7 +20717,7 @@
(match_operand:HI 2 "immediate_operand" "")))
(clobber (reg:CC FLAGS_REG))])
(match_scratch:HI 3 "r")]
"(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size"
"TARGET_SLOW_IMUL_IMM8 && !optimize_size"
[(set (match_dup 3) (match_dup 2))
(parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
(clobber (reg:CC FLAGS_REG))])]