re PR target/80206 (ICE in extract_insn, at recog.c:2327)
PR target/80206 * config/i386/sse.md (<extract_type>_vextract<shuffletype><extract_suf>_mask): Use register as dest whenever it is a MEM not rtx_equal_p to the corresponding dup operand, and when forcing into reg move the reg into the memory afterwards. (<extract_type_2>_vextract<shuffletype><extract_suf_2>_mask): Likewise. Use <ssehalfvecmode> instead of <ssequartermode> for the force_reg mode. (avx512vl_vextractf128<mode>): Use register as dest either always when a MEM, or when it is a MEM not rtx_equal_p to the corresponding dup operand, or even not when it is a CONST_VECTOR depending on the mode and lo vs. hi. (avx512dq_vextract<shuffletype>64x2_1_maskm): Remove extraneous parens. (avx512f_vextract<shuffletype>32x4_1_maskm): Likewise. (<mask_codefor>avx512dq_vextract<shuffletype>64x2_1<mask_name>): Likewise. Require that operands[2] is even. (<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>): Remove extraneous parens. Require that operands[2] is a multiple of 4. (vec_extract_lo_<mode><mask_name>): Don't bother testing if operands[0] is a MEM if <mask_applied>, the predicates/constraints disallow memory then. * gcc.target/i386/pr80206.c: New test. From-SVN: r246588
This commit is contained in:
Jakub Jelinek
Jakub Jelinek
parent
28c0240778
commit
de008ec4d6
@ -1,3 +1,30 @@
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2017-03-30 Jakub Jelinek <jakub@redhat.com>
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PR target/80206
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* config/i386/sse.md
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(<extract_type>_vextract<shuffletype><extract_suf>_mask): Use
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register as dest whenever it is a MEM not rtx_equal_p to the
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corresponding dup operand, and when forcing into reg move the
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reg into the memory afterwards.
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(<extract_type_2>_vextract<shuffletype><extract_suf_2>_mask):
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Likewise. Use <ssehalfvecmode> instead of <ssequartermode>
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for the force_reg mode.
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(avx512vl_vextractf128<mode>): Use register as dest either
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always when a MEM, or when it is a MEM not rtx_equal_p to the
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corresponding dup operand, or even not when it is a CONST_VECTOR
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depending on the mode and lo vs. hi.
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(avx512dq_vextract<shuffletype>64x2_1_maskm): Remove extraneous
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parens.
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(avx512f_vextract<shuffletype>32x4_1_maskm): Likewise.
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(<mask_codefor>avx512dq_vextract<shuffletype>64x2_1<mask_name>):
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Likewise. Require that operands[2] is even.
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(<mask_codefor>avx512f_vextract<shuffletype>32x4_1<mask_name>):
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Remove extraneous parens. Require that operands[2] is a multiple
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of 4.
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(vec_extract_lo_<mode><mask_name>): Don't bother testing if
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operands[0] is a MEM if <mask_applied>, the predicates/constraints
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disallow memory then.
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2017-03-30 Richard Biener <rguenther@suse.de>
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PR tree-optimization/77498
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@ -7135,19 +7135,22 @@
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{
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int mask;
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mask = INTVAL (operands[2]);
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rtx dest = operands[0];
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if (MEM_P (operands[0]) && GET_CODE (operands[3]) == CONST_VECTOR)
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operands[0] = force_reg (<ssequartermode>mode, operands[0]);
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if (MEM_P (operands[0]) && !rtx_equal_p (operands[0], operands[3]))
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dest = gen_reg_rtx (<ssequartermode>mode);
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if (<MODE>mode == V16SImode || <MODE>mode == V16SFmode)
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emit_insn (gen_avx512f_vextract<shuffletype>32x4_1_mask (operands[0],
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emit_insn (gen_avx512f_vextract<shuffletype>32x4_1_mask (dest,
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operands[1], GEN_INT (mask * 4), GEN_INT (mask * 4 + 1),
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GEN_INT (mask * 4 + 2), GEN_INT (mask * 4 + 3), operands[3],
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operands[4]));
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else
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emit_insn (gen_avx512dq_vextract<shuffletype>64x2_1_mask (operands[0],
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emit_insn (gen_avx512dq_vextract<shuffletype>64x2_1_mask (dest,
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operands[1], GEN_INT (mask * 2), GEN_INT (mask * 2 + 1), operands[3],
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operands[4]));
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if (dest != operands[0])
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emit_move_insn (operands[0], dest);
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DONE;
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})
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@ -7161,8 +7164,8 @@
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(match_operand:<ssequartermode> 4 "memory_operand" "0")
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(match_operand:QI 5 "register_operand" "Yk")))]
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"TARGET_AVX512DQ
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&& (INTVAL (operands[2]) % 2 == 0)
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&& (INTVAL (operands[2]) == INTVAL (operands[3]) - 1)
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&& INTVAL (operands[2]) % 2 == 0
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&& INTVAL (operands[2]) == INTVAL (operands[3]) - 1
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&& rtx_equal_p (operands[4], operands[0])"
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{
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operands[2] = GEN_INT ((INTVAL (operands[2])) >> 1);
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@ -7187,13 +7190,13 @@
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(match_operand:<ssequartermode> 6 "memory_operand" "0")
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(match_operand:QI 7 "register_operand" "Yk")))]
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"TARGET_AVX512F
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&& ((INTVAL (operands[2]) % 4 == 0)
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&& INTVAL (operands[2]) == (INTVAL (operands[3]) - 1)
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&& INTVAL (operands[3]) == (INTVAL (operands[4]) - 1)
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&& INTVAL (operands[4]) == (INTVAL (operands[5]) - 1))
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&& INTVAL (operands[2]) % 4 == 0
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&& INTVAL (operands[2]) == INTVAL (operands[3]) - 1
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&& INTVAL (operands[3]) == INTVAL (operands[4]) - 1
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&& INTVAL (operands[4]) == INTVAL (operands[5]) - 1
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&& rtx_equal_p (operands[6], operands[0])"
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{
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operands[2] = GEN_INT ((INTVAL (operands[2])) >> 2);
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operands[2] = GEN_INT (INTVAL (operands[2]) >> 2);
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return "vextract<shuffletype>32x4\t{%2, %1, %0%{%7%}|%0%{%7%}, %1, %2}";
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}
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[(set_attr "type" "sselog")
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@ -7209,9 +7212,11 @@
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(match_operand:V8FI 1 "register_operand" "v")
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(parallel [(match_operand 2 "const_0_to_7_operand")
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(match_operand 3 "const_0_to_7_operand")])))]
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"TARGET_AVX512DQ && (INTVAL (operands[2]) == INTVAL (operands[3]) - 1)"
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"TARGET_AVX512DQ
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&& INTVAL (operands[2]) % 2 == 0
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&& INTVAL (operands[2]) == INTVAL (operands[3]) - 1"
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{
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operands[2] = GEN_INT ((INTVAL (operands[2])) >> 1);
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operands[2] = GEN_INT (INTVAL (operands[2]) >> 1);
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return "vextract<shuffletype>64x2\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}";
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}
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[(set_attr "type" "sselog1")
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@ -7229,11 +7234,12 @@
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(match_operand 4 "const_0_to_15_operand")
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(match_operand 5 "const_0_to_15_operand")])))]
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"TARGET_AVX512F
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&& (INTVAL (operands[2]) == (INTVAL (operands[3]) - 1)
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&& INTVAL (operands[3]) == (INTVAL (operands[4]) - 1)
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&& INTVAL (operands[4]) == (INTVAL (operands[5]) - 1))"
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&& INTVAL (operands[2]) % 4 == 0
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&& INTVAL (operands[2]) == INTVAL (operands[3]) - 1
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&& INTVAL (operands[3]) == INTVAL (operands[4]) - 1
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&& INTVAL (operands[4]) == INTVAL (operands[5]) - 1"
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{
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operands[2] = GEN_INT ((INTVAL (operands[2])) >> 2);
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operands[2] = GEN_INT (INTVAL (operands[2]) >> 2);
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return "vextract<shuffletype>32x4\t{%2, %1, %0<mask_operand6>|%0<mask_operand6>, %1, %2}";
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}
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[(set_attr "type" "sselog1")
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@ -7260,9 +7266,10 @@
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"TARGET_AVX512F"
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{
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rtx (*insn)(rtx, rtx, rtx, rtx);
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rtx dest = operands[0];
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if (MEM_P (operands[0]) && GET_CODE (operands[3]) == CONST_VECTOR)
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operands[0] = force_reg (<ssequartermode>mode, operands[0]);
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if (MEM_P (dest) && !rtx_equal_p (dest, operands[3]))
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dest = gen_reg_rtx (<ssehalfvecmode>mode);
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switch (INTVAL (operands[2]))
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{
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@ -7276,7 +7283,9 @@
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gcc_unreachable ();
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}
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emit_insn (insn (operands[0], operands[1], operands[3], operands[4]));
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emit_insn (insn (dest, operands[1], operands[3], operands[4]));
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if (dest != operands[0])
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emit_move_insn (operands[0], dest);
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DONE;
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})
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@ -7317,7 +7326,8 @@
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(match_operand:V8FI 1 "nonimmediate_operand" "v,m")
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(parallel [(const_int 0) (const_int 1)
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(const_int 2) (const_int 3)])))]
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"TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"TARGET_AVX512F
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&& (<mask_applied> || !(MEM_P (operands[0]) && MEM_P (operands[1])))"
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{
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if (<mask_applied> || !TARGET_AVX512VL)
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return "vextract<shuffletype>64x4\t{$0x0, %1, %0<mask_operand2>|%0<mask_operand2>, %1, 0x0}";
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@ -7411,10 +7421,19 @@
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"TARGET_AVX512DQ && TARGET_AVX512VL"
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{
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rtx (*insn)(rtx, rtx, rtx, rtx);
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rtx dest = operands[0];
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if (MEM_P (operands[0]) && GET_CODE (operands[3]) == CONST_VECTOR)
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operands[0] = force_reg (<ssehalfvecmode>mode, operands[0]);
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if (MEM_P (dest)
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&& (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) == 4
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/* For V8S[IF]mode there are maskm insns with =m and 0
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constraints. */
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? !rtx_equal_p (dest, operands[3])
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/* For V4D[IF]mode, hi insns don't allow memory, and
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lo insns have =m and 0C constraints. */
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: (operands[2] != const0_rtx
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|| (!rtx_equal_p (dest, operands[3])
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&& GET_CODE (operands[3]) != CONST_VECTOR))))
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dest = gen_reg_rtx (<ssehalfvecmode>mode);
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switch (INTVAL (operands[2]))
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{
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case 0:
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@ -7427,7 +7446,9 @@
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gcc_unreachable ();
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}
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emit_insn (insn (operands[0], operands[1], operands[3], operands[4]));
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emit_insn (insn (dest, operands[1], operands[3], operands[4]));
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if (dest != operands[0])
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emit_move_insn (operands[0], dest);
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DONE;
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})
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@ -1,3 +1,8 @@
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2017-03-30 Jakub Jelinek <jakub@redhat.com>
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PR target/80206
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* gcc.target/i386/pr80206.c: New test.
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2017-03-30 Richard Biener <rguenther@suse.de>
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PR tree-optimization/77498
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14
gcc/testsuite/gcc.target/i386/pr80206.c
Normal file
14
gcc/testsuite/gcc.target/i386/pr80206.c
Normal file
@ -0,0 +1,14 @@
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/* PR target/80206 */
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/* { dg-do compile } */
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/* { dg-options "-mavx512f -ffloat-store" } */
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#include <immintrin.h>
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__m512d a;
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__m256d b;
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void
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foo (__m256d *p)
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{
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*p = _mm512_mask_extractf64x4_pd (b, 1, a, 1);
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}
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