rs6000.md (*rotlsi3_internal4, [...]): Delete, revamp, transmogrify into ...
* config/rs6000/rs6000.md (*rotlsi3_internal4, *rotlsi3_internal5, *rotlsi3_internal6, rlwinm, 5 unnamed define_insns, and 6 define_splits): Delete, revamp, transmogrify into ... (*rotlsi3_mask, *rotlsi3_mask_dot, *rotlsi3_mask_dot2, *ashlsi3_imm_mask, *ashlsi3_imm_mask_dot, *ashlsi3_imm_mask_dot2, *lshrsi3_imm_mask, *lshrsi3_imm_mask_dot, *lshrsi3_imm_mask_dot2): New. From-SVN: r223072
This commit is contained in:
parent
1a93ca861c
commit
de065fbf8d
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@ -1,3 +1,13 @@
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2015-05-12 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (*rotlsi3_internal4, *rotlsi3_internal5,
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*rotlsi3_internal6, rlwinm, 5 unnamed define_insns, and 6
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define_splits): Delete, revamp, transmogrify into ...
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(*rotlsi3_mask, *rotlsi3_mask_dot, *rotlsi3_mask_dot2,
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*ashlsi3_imm_mask, *ashlsi3_imm_mask_dot, *ashlsi3_imm_mask_dot2,
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*lshrsi3_imm_mask, *lshrsi3_imm_mask_dot, *lshrsi3_imm_mask_dot2):
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New.
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2015-05-12 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (rs6000_adjust_atomic_subword): Use
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@ -3745,7 +3745,7 @@
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(set_attr "length" "4,8")])
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(define_insn "*rotlsi3_internal4"
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(define_insn "*rotlsi3_mask"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "reg_or_cint_operand" "rn"))
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@ -3755,75 +3755,62 @@
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[(set_attr "type" "shift")
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(set_attr "maybe_var_shift" "yes")])
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(define_insn "*rotlsi3_internal5"
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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(compare:CC (and:SI
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(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(clobber (match_scratch:SI 4 "=r,r"))]
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""
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"@
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rlw%I2nm. %4,%1,%h2,%m3,%M3
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#"
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[(set_attr "type" "shift")
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(set_attr "maybe_var_shift" "yes")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC (and:SI
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(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_cint_operand" ""))
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(match_operand:SI 3 "mask_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 4 ""))]
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"reload_completed"
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[(set (match_dup 4)
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(and:SI (rotate:SI (match_dup 1)
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(match_dup 2))
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(match_dup 3)))
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(set (match_dup 0)
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(compare:CC (match_dup 4)
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(const_int 0)))]
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"")
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(define_insn "*rotlsi3_internal6"
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(define_insn_and_split "*rotlsi3_mask_dot"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC (and:SI
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(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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""
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(compare:CC
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(and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(clobber (match_scratch:SI 0 "=r,r"))]
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"rs6000_gen_cell_microcode
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&& (TARGET_32BIT || UINTVAL (operands[3]) <= 0x7fffffff)"
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"@
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rlw%I2nm. %0,%1,%h2,%m3,%M3
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#"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
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[(set (match_dup 0)
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(and:SI (rotate:SI (match_dup 1)
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(match_dup 2))
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(match_dup 3)))
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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""
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[(set_attr "type" "shift")
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(set_attr "maybe_var_shift" "yes")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_split
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[(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC (and:SI
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(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "reg_or_cint_operand" ""))
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(match_operand:SI 3 "mask_operand" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"reload_completed"
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(define_insn_and_split "*rotlsi3_mask_dot2"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC
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(and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(and:SI (rotate:SI (match_dup 1)
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(match_dup 2))
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(match_dup 3)))]
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"rs6000_gen_cell_microcode
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&& (TARGET_32BIT || UINTVAL (operands[3]) <= 0x7fffffff)"
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"@
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rlw%I2nm. %0,%1,%h2,%m3,%M3
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#"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
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[(set (match_dup 0)
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(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(and:SI (rotate:SI (match_dup 1)
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(match_dup 2))
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(match_dup 3)))
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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""
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[(set_attr "type" "shift")
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(set_attr "maybe_var_shift" "yes")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_insn "ashl<mode>3"
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@ -3894,7 +3881,7 @@
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(set_attr "length" "4,8")])
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(define_insn "rlwinm"
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(define_insn "*ashlsi3_imm_mask"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i"))
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@ -3903,40 +3890,34 @@
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"rlwinm %0,%1,%h2,%m3,%M3"
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[(set_attr "type" "shift")])
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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(define_insn_and_split "*ashlsi3_imm_mask_dot"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC
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(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "const_int_operand" "i,i"))
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(clobber (match_scratch:SI 4 "=r,r"))]
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"includes_lshift_p (operands[2], operands[3])"
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(clobber (match_scratch:SI 0 "=r,r"))]
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"rs6000_gen_cell_microcode
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&& (TARGET_32BIT || UINTVAL (operands[3]) <= 0x7fffffff)
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&& includes_lshift_p (operands[2], operands[3])"
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"@
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rlwinm. %4,%1,%h2,%m3,%M3
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rlwinm. %0,%1,%h2,%m3,%M3
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#"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
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[(set (match_dup 0)
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(and:SI (ashift:SI (match_dup 1)
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(match_dup 2))
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(match_dup 3)))
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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""
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[(set_attr "type" "shift")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC
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(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "const_int_operand" ""))
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(match_operand:SI 3 "mask_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 4 ""))]
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"includes_lshift_p (operands[2], operands[3]) && reload_completed"
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[(set (match_dup 4)
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(and:SI (ashift:SI (match_dup 1) (match_dup 2))
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(match_dup 3)))
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(set (match_dup 0)
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(compare:CC (match_dup 4)
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(const_int 0)))]
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"")
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(define_insn ""
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(define_insn_and_split "*ashlsi3_imm_mask_dot2"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC
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(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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@ -3944,31 +3925,27 @@
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"includes_lshift_p (operands[2], operands[3])"
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(and:SI (ashift:SI (match_dup 1)
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(match_dup 2))
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(match_dup 3)))]
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"rs6000_gen_cell_microcode
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&& (TARGET_32BIT || UINTVAL (operands[3]) <= 0x7fffffff)
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&& includes_lshift_p (operands[2], operands[3])"
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"@
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rlwinm. %0,%1,%h2,%m3,%M3
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#"
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[(set_attr "type" "shift")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_split
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[(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC
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(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "const_int_operand" ""))
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(match_operand:SI 3 "mask_operand" ""))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
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"includes_lshift_p (operands[2], operands[3]) && reload_completed"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
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[(set (match_dup 0)
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(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(and:SI (ashift:SI (match_dup 1)
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(match_dup 2))
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(match_dup 3)))
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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"")
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""
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[(set_attr "type" "shift")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_insn "lshr<mode>3"
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@ -4039,7 +4016,7 @@
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(set_attr "length" "4,8")])
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(define_insn ""
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(define_insn "*lshrsi3_imm_mask"
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[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
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(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
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(match_operand:SI 2 "const_int_operand" "i"))
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@ -4048,40 +4025,34 @@
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"rlwinm %0,%1,%s2,%m3,%M3"
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[(set_attr "type" "shift")])
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(define_insn ""
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[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
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(define_insn_and_split "*lshrsi3_imm_mask_dot"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC
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(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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(match_operand:SI 2 "const_int_operand" "i,i"))
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(clobber (match_scratch:SI 4 "=r,r"))]
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"includes_rshift_p (operands[2], operands[3])"
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(clobber (match_scratch:SI 0 "=r,r"))]
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"rs6000_gen_cell_microcode
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&& (TARGET_32BIT || UINTVAL (operands[3]) <= 0x7fffffff)
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&& includes_rshift_p (operands[2], operands[3])"
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"@
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rlwinm. %4,%1,%s2,%m3,%M3
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rlwinm. %0,%1,%s2,%m3,%M3
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#"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
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[(set (match_dup 0)
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(and:SI (lshiftrt:SI (match_dup 1)
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(match_dup 2))
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(match_dup 3)))
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(set (match_dup 4)
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(compare:CC (match_dup 0)
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(const_int 0)))]
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""
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[(set_attr "type" "shift")
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(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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(define_split
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[(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC
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(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "const_int_operand" ""))
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(match_operand:SI 3 "mask_operand" ""))
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(const_int 0)))
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(clobber (match_scratch:SI 4 ""))]
|
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"includes_rshift_p (operands[2], operands[3]) && reload_completed"
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[(set (match_dup 4)
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(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
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(match_dup 3)))
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(set (match_dup 0)
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(compare:CC (match_dup 4)
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(const_int 0)))]
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"")
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(define_insn ""
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(define_insn_and_split "*lshrsi3_imm_mask_dot2"
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[(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
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(compare:CC
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(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
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|
@ -4089,31 +4060,27 @@
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(match_operand:SI 3 "mask_operand" "n,n"))
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
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(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"includes_rshift_p (operands[2], operands[3])"
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(and:SI (lshiftrt:SI (match_dup 1)
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(match_dup 2))
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(match_dup 3)))]
|
||||
"rs6000_gen_cell_microcode
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&& (TARGET_32BIT || UINTVAL (operands[3]) <= 0x7fffffff)
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&& includes_rshift_p (operands[2], operands[3])"
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"@
|
||||
rlwinm. %0,%1,%s2,%m3,%M3
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||||
#"
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[(set_attr "type" "shift")
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||||
(set_attr "dot" "yes")
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(set_attr "length" "4,8")])
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|
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(define_split
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[(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
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(compare:CC
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(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
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(match_operand:SI 2 "const_int_operand" ""))
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(match_operand:SI 3 "mask_operand" ""))
|
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(const_int 0)))
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(set (match_operand:SI 0 "gpc_reg_operand" "")
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(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
|
||||
"includes_rshift_p (operands[2], operands[3]) && reload_completed"
|
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"&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
|
||||
[(set (match_dup 0)
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||||
(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
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(and:SI (lshiftrt:SI (match_dup 1)
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(match_dup 2))
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(match_dup 3)))
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(set (match_dup 4)
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(compare:CC (match_dup 0)
|
||||
(const_int 0)))]
|
||||
"")
|
||||
""
|
||||
[(set_attr "type" "shift")
|
||||
(set_attr "dot" "yes")
|
||||
(set_attr "length" "4,8")])
|
||||
|
||||
|
||||
(define_expand "ashr<mode>3"
|
||||
|
|
Loading…
Reference in New Issue