re PR target/19019 (GCC ldouble format incompatibility with XLC long double)
PR target/19019 * config/rs6000/aix.h ({TARGET,MASK}_XL_CALL): Rename to {TARGET,MASK}_XL_COMPAT. (SUBTARGET_SWITCHES): Rename xl-call to xl-compat. Use MASK_XL_COMPAT. * config/rs6000/beos.h ({TARGET,MASK}_XL_CALL): Remove. * config/rs6000/rs6000.c (function_arg): Change TARGET_XL_CALL to TARGET_XL_COMPAT. (rs6000_arg_partial_bytes): Same. (rs6000_generate_compare): Generate PARALLEL for compare if TFmode and XL compatibility enabled. * config/rs6000/rs6000.h (TARGET_XL_CALL): Rename to TARGET_XL_COMPAT. * config/rs6000/rs6000.md (cmptf_internal1): Add !TARGET_XL_COMPAT test to final condition. (cmptf_internal2): New. * doc/invoke.texi (RS/6000 Subtarget Options): Change xl-call to xl-compat. Add TFmode information to description. From-SVN: r94991
This commit is contained in:
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@ -1,3 +1,23 @@
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2005-02-13 David Edelsohn <edelsohn@gnu.org>
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PR target/19019
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* config/rs6000/aix.h ({TARGET,MASK}_XL_CALL): Rename to
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{TARGET,MASK}_XL_COMPAT.
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(SUBTARGET_SWITCHES): Rename xl-call to xl-compat. Use
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MASK_XL_COMPAT.
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* config/rs6000/beos.h ({TARGET,MASK}_XL_CALL): Remove.
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* config/rs6000/rs6000.c (function_arg): Change TARGET_XL_CALL to
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TARGET_XL_COMPAT.
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(rs6000_arg_partial_bytes): Same.
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(rs6000_generate_compare): Generate PARALLEL for compare if TFmode
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and XL compatibility enabled.
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* config/rs6000/rs6000.h (TARGET_XL_CALL): Rename to TARGET_XL_COMPAT.
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* config/rs6000/rs6000.md (cmptf_internal1): Add !TARGET_XL_COMPAT
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test to final condition.
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(cmptf_internal2): New.
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* doc/invoke.texi (RS/6000 Subtarget Options): Change xl-call to
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xl-compat. Add TFmode information to description.
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2005-02-13 Kazu Hirata <kazu@cs.umass.edu>
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2005-02-13 Kazu Hirata <kazu@cs.umass.edu>
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* flags.h, read-rtl.c, tree-ssa-live.h: Update copyright.
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* flags.h, read-rtl.c, tree-ssa-live.h: Update copyright.
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@ -194,15 +194,15 @@
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#define JUMP_TABLES_IN_TEXT_SECTION 1
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#define JUMP_TABLES_IN_TEXT_SECTION 1
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/* Enable AIX XL compiler calling convention breakage compatibility. */
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/* Enable AIX XL compiler calling convention breakage compatibility. */
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#undef TARGET_XL_CALL
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#undef TARGET_XL_COMPAT
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#define MASK_XL_CALL 0x40000000
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#define MASK_XL_COMPAT 0x40000000
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#define TARGET_XL_CALL (target_flags & MASK_XL_CALL)
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#define TARGET_XL_COMPAT (target_flags & MASK_XL_COMPAT)
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#undef SUBTARGET_SWITCHES
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#undef SUBTARGET_SWITCHES
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#define SUBTARGET_SWITCHES \
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#define SUBTARGET_SWITCHES \
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{"xl-call", MASK_XL_CALL, \
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{"xl-compat", MASK_XL_COMPAT, \
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N_("Always pass floating-point arguments in memory") }, \
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N_("Conform more closely to IBM XLC semantics") }, \
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{"no-xl-call", - MASK_XL_CALL, \
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{"no-xl-compat", - MASK_XL_COMPAT, \
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N_("Don't always pass floating-point arguments in memory") }, \
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N_("Default GCC semantics that differ from IBM XLC") }, \
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SUBSUBTARGET_SWITCHES
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SUBSUBTARGET_SWITCHES
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#define SUBSUBTARGET_SWITCHES
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#define SUBSUBTARGET_SWITCHES
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@ -23,18 +23,6 @@
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#undef TARGET_VERSION
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#undef TARGET_VERSION
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#define TARGET_VERSION fprintf (stderr, " (BeOS/PowerPC)");
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#define TARGET_VERSION fprintf (stderr, " (BeOS/PowerPC)");
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/* Enable AIX XL compiler calling convention breakage compatibility. */
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#define MASK_XL_CALL 0x40000000
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#define TARGET_XL_CALL (target_flags & MASK_XL_CALL)
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#undef SUBTARGET_SWITCHES
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#define SUBTARGET_SWITCHES \
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{"xl-call", MASK_XL_CALL, \
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N_("Always pass floating-point arguments in memory") }, \
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{"no-xl-call", - MASK_XL_CALL, \
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N_("Don't always pass floating-point arguments in memory") }, \
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{"threads", 0}, \
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{"pe", 0},
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#undef ASM_SPEC
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#undef ASM_SPEC
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#define ASM_SPEC "-u %(asm_cpu)"
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#define ASM_SPEC "-u %(asm_cpu)"
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@ -5604,7 +5604,7 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
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needs_psave = (type
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needs_psave = (type
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&& (cum->nargs_prototype <= 0
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&& (cum->nargs_prototype <= 0
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|| (DEFAULT_ABI == ABI_AIX
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|| (DEFAULT_ABI == ABI_AIX
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&& TARGET_XL_CALL
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&& TARGET_XL_COMPAT
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&& align_words >= GP_ARG_NUM_REG)));
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&& align_words >= GP_ARG_NUM_REG)));
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if (!needs_psave && mode == fmode)
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if (!needs_psave && mode == fmode)
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@ -5712,7 +5712,7 @@ rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
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&& !(type
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&& !(type
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&& (cum->nargs_prototype <= 0
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&& (cum->nargs_prototype <= 0
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|| (DEFAULT_ABI == ABI_AIX
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|| (DEFAULT_ABI == ABI_AIX
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&& TARGET_XL_CALL
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&& TARGET_XL_COMPAT
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&& align_words >= GP_ARG_NUM_REG))))
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&& align_words >= GP_ARG_NUM_REG))))
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{
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{
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if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
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if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
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@ -11458,10 +11458,34 @@ rs6000_generate_compare (enum rtx_code code)
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emit_insn (cmp);
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emit_insn (cmp);
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}
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}
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else
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else
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emit_insn (gen_rtx_SET (VOIDmode, compare_result,
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{
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gen_rtx_COMPARE (comp_mode,
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/* Generate XLC-compatible TFmode compare as PARALLEL with extra
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rs6000_compare_op0,
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CLOBBERs to match cmptf_internal2 pattern. */
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rs6000_compare_op1)));
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if (comp_mode == CCFPmode && TARGET_XL_COMPAT
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&& GET_MODE (rs6000_compare_op0) == TFmode
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&& (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
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&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
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emit_insn (gen_rtx_PARALLEL (VOIDmode,
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gen_rtvec (9,
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gen_rtx_SET (VOIDmode,
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compare_result,
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gen_rtx_COMPARE (comp_mode,
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rs6000_compare_op0,
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rs6000_compare_op1)),
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
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gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
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else
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emit_insn (gen_rtx_SET (VOIDmode, compare_result,
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gen_rtx_COMPARE (comp_mode,
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rs6000_compare_op0,
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rs6000_compare_op1)));
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}
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/* Some kinds of FP comparisons need an OR operation;
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/* Some kinds of FP comparisons need an OR operation;
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under flag_unsafe_math_optimizations we don't bother. */
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under flag_unsafe_math_optimizations we don't bother. */
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@ -262,7 +262,7 @@ extern int target_flags;
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#define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
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#define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
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#endif
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#endif
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#define TARGET_XL_CALL 0
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#define TARGET_XL_COMPAT 0
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/* Run-time compilation parameters selecting different hardware subsets.
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/* Run-time compilation parameters selecting different hardware subsets.
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@ -11364,11 +11364,70 @@
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[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
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[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
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(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
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(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
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(match_operand:TF 2 "gpc_reg_operand" "f")))]
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(match_operand:TF 2 "gpc_reg_operand" "f")))]
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"(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
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"(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT
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&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
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&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
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"fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
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"fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
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[(set_attr "type" "fpcompare")
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[(set_attr "type" "fpcompare")
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(set_attr "length" "12")])
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(set_attr "length" "12")])
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(define_insn_and_split "*cmptf_internal2"
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[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
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(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
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(match_operand:TF 2 "gpc_reg_operand" "f")))
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(clobber (match_scratch:DF 3 "=f"))
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(clobber (match_scratch:DF 4 "=f"))
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(clobber (match_scratch:DF 5 "=f"))
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(clobber (match_scratch:DF 6 "=f"))
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(clobber (match_scratch:DF 7 "=f"))
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(clobber (match_scratch:DF 8 "=f"))
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(clobber (match_scratch:DF 9 "=f"))
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(clobber (match_scratch:DF 10 "=f"))]
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"(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT
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&& TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
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"#"
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"&& reload_completed"
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[(set (match_dup 3) (match_dup 13))
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(set (match_dup 4) (match_dup 14))
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(set (match_dup 9) (abs:DF (match_dup 5)))
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(set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
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(set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
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(label_ref (match_dup 11))
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(pc)))
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(set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
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(set (pc) (label_ref (match_dup 12)))
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(match_dup 11)
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(set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
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(set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
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(set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
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(set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
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(match_dup 12)]
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{
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REAL_VALUE_TYPE rv;
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const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
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const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
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operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
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operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
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operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
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operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
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operands[11] = gen_label_rtx ();
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operands[12] = gen_label_rtx ();
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real_inf (&rv);
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operands[13] = force_const_mem (DFmode,
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CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
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operands[14] = force_const_mem (DFmode,
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CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
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DFmode));
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if (TARGET_TOC)
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{
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operands[13] = gen_const_mem (DFmode,
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create_TOC_reference (XEXP (operands[13], 0)));
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operands[14] = gen_const_mem (DFmode,
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create_TOC_reference (XEXP (operands[14], 0)));
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set_mem_alias_set (operands[13], get_TOC_alias_set ());
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set_mem_alias_set (operands[14], get_TOC_alias_set ());
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}
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})
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;; Now we have the scc insns. We can do some combinations because of the
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;; Now we have the scc insns. We can do some combinations because of the
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;; way the machine works.
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;; way the machine works.
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@ -602,7 +602,7 @@ See RS/6000 and PowerPC Options.
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-mpowerpc-gfxopt -mno-powerpc-gfxopt @gol
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-mpowerpc-gfxopt -mno-powerpc-gfxopt @gol
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-mnew-mnemonics -mold-mnemonics @gol
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-mnew-mnemonics -mold-mnemonics @gol
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-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol
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-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol
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-m64 -m32 -mxl-call -mno-xl-call -mpe @gol
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-m64 -m32 -mxl-compat -mno-xl-compat -mpe @gol
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-malign-power -malign-natural @gol
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-malign-power -malign-natural @gol
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-msoft-float -mhard-float -mmultiple -mno-multiple @gol
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-msoft-float -mhard-float -mmultiple -mno-multiple @gol
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-mstring -mno-string -mupdate -mno-update @gol
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-mstring -mno-string -mupdate -mno-update @gol
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@option{-mpowerpc}, while @option{-maix32} disables the 64-bit ABI and
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@option{-mpowerpc}, while @option{-maix32} disables the 64-bit ABI and
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implies @option{-mno-powerpc64}. GCC defaults to @option{-maix32}.
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implies @option{-mno-powerpc64}. GCC defaults to @option{-maix32}.
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@item -mxl-call
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@item -mxl-compat
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@itemx -mno-xl-call
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@itemx -mno-xl-compat
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@opindex mxl-call
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@opindex mxl-compat
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@opindex mno-xl-call
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@opindex mno-xl-compat
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On AIX, pass floating-point arguments to prototyped functions beyond the
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Produce code that conforms more closely to IBM XLC semantics when using
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register save area (RSA) on the stack in addition to argument FPRs. The
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AIX-compatible ABI. Pass floating-point arguments to prototyped
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AIX calling convention was extended but not initially documented to
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functions beyond the register save area (RSA) on the stack in addition
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to argument FPRs. Do not assume that most significant double in 128
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bit long double value is properly rounded when comparing values.
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The AIX calling convention was extended but not initially documented to
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handle an obscure K&R C case of calling a function that takes the
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handle an obscure K&R C case of calling a function that takes the
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address of its arguments with fewer arguments than declared. AIX XL
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address of its arguments with fewer arguments than declared. AIX XL
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compilers access floating point arguments which do not fit in the
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compilers access floating point arguments which do not fit in the
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