alpha.h (MASK_FIX, TARGET_FIX): New.
* alpha.h (MASK_FIX, TARGET_FIX): New.
(MASK_*): Reorganize constants.
(CPP_AM_FIX_SPEC): New.
(TARGET_SWITCHES): Add FIX.
(EXTRA_SPECS): Likewise.
(CPP_CPU_EV6_SPEC): Use FIX, not CIX.
(SECONDARY_MEMORY_NEEDED): Likewise.
(REGISTER_MOVE_COST): Likewise.
* alpha.c (override_options): Add FIX support. Always use
ALPHA_TP_PROG for ev6.
* alpha.md (sqrt and mov[sd]i patterns): Use FIX, not CIX.
* alpha/elf.h (ASM_FILE_START): Look at FIX too.
* configure.in (target_cpu_default2) [ev6]: Use FIX, not CIX.
From-SVN: r27183
This commit is contained in:
Richard Henderson
Richard Henderson
parent
2ba1f15fb9
commit
de4abb91d1
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@ -1,3 +1,19 @@
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Wed May 26 14:18:05 1999 Richard Henderson <rth@cygnus.com>
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* alpha.h (MASK_FIX, TARGET_FIX): New.
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(MASK_*): Reorganize constants.
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(CPP_AM_FIX_SPEC): New.
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(TARGET_SWITCHES): Add FIX.
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(EXTRA_SPECS): Likewise.
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(CPP_CPU_EV6_SPEC): Use FIX, not CIX.
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(SECONDARY_MEMORY_NEEDED): Likewise.
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(REGISTER_MOVE_COST): Likewise.
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* alpha.c (override_options): Add FIX support. Always use
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ALPHA_TP_PROG for ev6.
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* alpha.md (sqrt and mov[sd]i patterns): Use FIX, not CIX.
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* alpha/elf.h (ASM_FILE_START): Look at FIX too.
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* configure.in (target_cpu_default2) [ev6]: Use FIX, not CIX.
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Wed May 26 09:53:05 1999 Mark Mitchell <mark@codesourcery.com>
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* fold-const.c (fold): STRIP_NOPS when deciding whether or not
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@ -134,49 +134,6 @@ static int alpha_does_function_need_gp
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void
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override_options ()
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{
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alpha_cpu
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= TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
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: (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
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if (alpha_cpu_string)
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{
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if (! strcmp (alpha_cpu_string, "ev4")
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|| ! strcmp (alpha_cpu_string, "21064"))
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{
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alpha_cpu = PROCESSOR_EV4;
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target_flags &= ~ (MASK_BWX | MASK_CIX | MASK_MAX);
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}
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else if (! strcmp (alpha_cpu_string, "ev5")
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|| ! strcmp (alpha_cpu_string, "21164"))
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{
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alpha_cpu = PROCESSOR_EV5;
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target_flags &= ~ (MASK_BWX | MASK_CIX | MASK_MAX);
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}
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else if (! strcmp (alpha_cpu_string, "ev56")
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|| ! strcmp (alpha_cpu_string, "21164a"))
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{
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alpha_cpu = PROCESSOR_EV5;
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target_flags |= MASK_BWX;
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target_flags &= ~ (MASK_CIX | MASK_MAX);
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}
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else if (! strcmp (alpha_cpu_string, "pca56")
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|| ! strcmp (alpha_cpu_string, "21164PC")
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|| ! strcmp (alpha_cpu_string, "21164pc"))
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{
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alpha_cpu = PROCESSOR_EV5;
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target_flags |= MASK_BWX | MASK_MAX;
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target_flags &= ~ MASK_CIX;
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}
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else if (! strcmp (alpha_cpu_string, "ev6")
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|| ! strcmp (alpha_cpu_string, "21264"))
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{
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alpha_cpu = PROCESSOR_EV6;
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target_flags |= MASK_BWX | MASK_CIX | MASK_MAX;
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}
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else
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error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
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}
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alpha_tp = ALPHA_TP_PROG;
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alpha_fprm = ALPHA_FPRM_NORM;
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alpha_fptm = ALPHA_FPTM_N;
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@ -234,10 +191,59 @@ override_options ()
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error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
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}
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/* Do some sanity checks on the above option. */
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alpha_cpu
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= TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
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: (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
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if (alpha_cpu_string)
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{
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if (! strcmp (alpha_cpu_string, "ev4")
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|| ! strcmp (alpha_cpu_string, "21064"))
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{
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alpha_cpu = PROCESSOR_EV4;
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target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX);
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}
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else if (! strcmp (alpha_cpu_string, "ev5")
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|| ! strcmp (alpha_cpu_string, "21164"))
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{
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alpha_cpu = PROCESSOR_EV5;
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target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX);
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}
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else if (! strcmp (alpha_cpu_string, "ev56")
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|| ! strcmp (alpha_cpu_string, "21164a"))
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{
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alpha_cpu = PROCESSOR_EV5;
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target_flags |= MASK_BWX;
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target_flags &= ~ (MASK_MAX | MASK_FIX | MASK_CIX);
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}
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else if (! strcmp (alpha_cpu_string, "pca56")
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|| ! strcmp (alpha_cpu_string, "21164PC")
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|| ! strcmp (alpha_cpu_string, "21164pc"))
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{
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alpha_cpu = PROCESSOR_EV5;
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target_flags |= MASK_BWX | MASK_MAX;
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target_flags &= ~ (MASK_FIX | MASK_CIX);
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}
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else if (! strcmp (alpha_cpu_string, "ev6")
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|| ! strcmp (alpha_cpu_string, "21264"))
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{
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alpha_cpu = PROCESSOR_EV6;
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target_flags |= MASK_BWX | MASK_MAX | MASK_FIX;
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target_flags &= ~ (MASK_CIX);
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/* Except for EV6 pass 1 (not released), we always have
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precise arithmetic traps. Which means we can do
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software completion without minding trap shadows. */
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alpha_tp = ALPHA_TP_PROG;
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}
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else
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error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
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}
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/* Do some sanity checks on the above options. */
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if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
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&& alpha_tp != ALPHA_TP_INSN)
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&& (alpha_tp != ALPHA_TP_INSN || alpha_cpu == PROCESSOR_EV6))
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{
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warning ("fp software completion requires -mtrap-precision=i");
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alpha_tp = ALPHA_TP_INSN;
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@ -95,73 +95,76 @@ extern enum alpha_fp_trap_mode alpha_fptm;
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/* This means that floating-point support exists in the target implementation
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of the Alpha architecture. This is usually the default. */
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#define MASK_FP 1
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#define MASK_FP (1 << 0)
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#define TARGET_FP (target_flags & MASK_FP)
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/* This means that floating-point registers are allowed to be used. Note
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that Alpha implementations without FP operations are required to
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provide the FP registers. */
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#define MASK_FPREGS 2
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#define MASK_FPREGS (1 << 1)
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#define TARGET_FPREGS (target_flags & MASK_FPREGS)
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/* This means that gas is used to process the assembler file. */
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#define MASK_GAS 4
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#define MASK_GAS (1 << 2)
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#define TARGET_GAS (target_flags & MASK_GAS)
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/* This means that we should mark procedures as IEEE conformant. */
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#define MASK_IEEE_CONFORMANT 8
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#define MASK_IEEE_CONFORMANT (1 << 3)
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#define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
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/* This means we should be IEEE-compliant except for inexact. */
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#define MASK_IEEE 16
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#define MASK_IEEE (1 << 4)
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#define TARGET_IEEE (target_flags & MASK_IEEE)
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/* This means we should be fully IEEE-compliant. */
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#define MASK_IEEE_WITH_INEXACT 32
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#define MASK_IEEE_WITH_INEXACT (1 << 5)
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#define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
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/* This means we must construct all constants rather than emitting
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them as literal data. */
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#define MASK_BUILD_CONSTANTS 128
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#define MASK_BUILD_CONSTANTS (1 << 6)
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#define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
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/* This means we handle floating points in VAX F- (float)
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or G- (double) Format. */
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#define MASK_FLOAT_VAX 512
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#define MASK_FLOAT_VAX (1 << 7)
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#define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
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/* This means that the processor has byte and half word loads and stores
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(the BWX extension). */
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#define MASK_BWX 1024
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#define MASK_BWX (1 << 8)
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#define TARGET_BWX (target_flags & MASK_BWX)
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/* This means that the processor has the CIX extension. */
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#define MASK_CIX 2048
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#define TARGET_CIX (target_flags & MASK_CIX)
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/* This means that the processor has the MAX extension. */
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#define MASK_MAX 4096
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#define MASK_MAX (1 << 9)
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#define TARGET_MAX (target_flags & MASK_MAX)
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/* This means that the processor has the FIX extension. */
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#define MASK_FIX (1 << 10)
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#define TARGET_FIX (target_flags & MASK_FIX)
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/* This means that the processor has the CIX extension. */
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#define MASK_CIX (1 << 11)
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#define TARGET_CIX (target_flags & MASK_CIX)
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/* This means that the processor is an EV5, EV56, or PCA56. This is defined
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only in TARGET_CPU_DEFAULT. */
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#define MASK_CPU_EV5 8192
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#define MASK_CPU_EV5 (1 << 29)
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/* Likewise for EV6. */
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#define MASK_CPU_EV6 16384
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#define MASK_CPU_EV6 (1 << 30)
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/* This means we support the .arch directive in the assembler. Only
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defined in TARGET_CPU_DEFAULT. */
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#define MASK_SUPPORT_ARCH 32768
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#define MASK_SUPPORT_ARCH (1 << 31)
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#define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
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/* These are for target os support and cannot be changed at runtime. */
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@ -204,10 +207,12 @@ extern enum alpha_fp_trap_mode alpha_fptm;
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{"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"}, \
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{"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"}, \
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{"no-bwx", -MASK_BWX, ""}, \
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{"cix", MASK_CIX, "Emit code for the counting ISA extension"}, \
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{"no-cix", -MASK_CIX, ""}, \
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{"max", MASK_MAX, "Emit code for the motion video ISA extension"}, \
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{"no-max", -MASK_MAX, ""}, \
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{"fix", MASK_FIX, "Emit code for the fp move and sqrt ISA extension"}, \
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{"no-fix", -MASK_FIX, ""}, \
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{"cix", MASK_CIX, "Emit code for the counting ISA extension"}, \
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{"no-cix", -MASK_CIX, ""}, \
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{"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
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#define TARGET_DEFAULT MASK_FP|MASK_FPREGS
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@ -258,6 +263,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */
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/* Corresponding to amask... */
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#define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu(bwx)"
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#define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu(max)"
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#define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu(fix)"
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#define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu(cix)"
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/* Corresponding to implver... */
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@ -270,7 +276,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */
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#define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)"
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#define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)"
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#define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
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#define CPP_CPU_EV6_SPEC "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_cix)"
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#define CPP_CPU_EV6_SPEC "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix)"
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#ifndef CPP_CPU_DEFAULT_SPEC
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# if TARGET_CPU_DEFAULT & MASK_CPU_EV6
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@ -320,6 +326,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */
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#define EXTRA_SPECS \
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{ "cpp_am_bwx", CPP_AM_BWX_SPEC }, \
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{ "cpp_am_max", CPP_AM_MAX_SPEC }, \
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{ "cpp_am_fix", CPP_AM_FIX_SPEC }, \
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{ "cpp_am_cix", CPP_AM_CIX_SPEC }, \
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{ "cpp_im_ev4", CPP_IM_EV4_SPEC }, \
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{ "cpp_im_ev5", CPP_IM_EV5_SPEC }, \
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@ -848,10 +855,10 @@ extern int normal_memory_operand ();
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: NO_REGS)
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/* If we are copying between general and FP registers, we need a memory
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location unless the CIX extension is available. */
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location unless the FIX extension is available. */
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#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
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(! TARGET_CIX && (CLASS1) != (CLASS2))
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(! TARGET_FIX && (CLASS1) != (CLASS2))
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/* Specify the mode to be used for memory when a secondary memory
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location is needed. If MODE is floating-point, use it. Otherwise,
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|
|
@ -884,7 +891,7 @@ extern int normal_memory_operand ();
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#define REGISTER_MOVE_COST(CLASS1, CLASS2) \
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(((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
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? 2 \
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: TARGET_CIX ? 3 : 4+2*alpha_memory_latency)
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: TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
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/* A C expressions returning the cost of moving data of MODE from a register to
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or from memory.
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|
|
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|
@ -1219,7 +1219,15 @@
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"eqv %r1,%2,%0"
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[(set_attr "type" "ilog")])
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;; Handle the FFS insn if we support CIX.
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;; Handle the FFS insn iff we support CIX.
|
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;;
|
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;; These didn't make it into EV6 pass 2 as planned. Instead they
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;; cropped cttz/ctlz/ctpop from the old CIX and renamed it FIX for
|
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;; "Square Root and Floating Point Convert Extension".
|
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;;
|
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;; I'm assured that these insns will make it into EV67 (first pass
|
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;; due Summer 1999), presumably with a new AMASK bit, and presumably
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;; will still be named CIX.
|
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|
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(define_expand "ffsdi2"
|
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[(set (match_dup 2)
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|
|
@ -1241,7 +1249,7 @@
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(unspec [(match_operand:DI 1 "register_operand" "r")] 1))]
|
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"TARGET_CIX"
|
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"cttz %1,%0"
|
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; ev6 calls all mvi and cttz/ctlz/popc class imisc, so just
|
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; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
|
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; reuse the existing type name.
|
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[(set_attr "type" "mvi")])
|
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|
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|
|
@ -2300,7 +2308,7 @@
|
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(define_insn ""
|
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[(set (match_operand:SF 0 "register_operand" "=&f")
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(sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
|
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"TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN"
|
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"TARGET_FP && TARGET_FIX && alpha_tp == ALPHA_TP_INSN"
|
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"sqrt%,%)%& %R1,%0"
|
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[(set_attr "type" "fsqrt")
|
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(set_attr "opsize" "si")
|
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|
|
@ -2309,7 +2317,7 @@
|
|||
(define_insn "sqrtsf2"
|
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[(set (match_operand:SF 0 "register_operand" "=f")
|
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(sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
|
||||
"TARGET_FP && TARGET_CIX"
|
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"TARGET_FP && TARGET_FIX"
|
||||
"sqrt%,%)%& %R1,%0"
|
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[(set_attr "type" "fsqrt")
|
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(set_attr "opsize" "si")
|
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|
|
@ -2318,7 +2326,7 @@
|
|||
(define_insn ""
|
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[(set (match_operand:DF 0 "register_operand" "=&f")
|
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(sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
|
||||
"TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN"
|
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"TARGET_FP && TARGET_FIX && alpha_tp == ALPHA_TP_INSN"
|
||||
"sqrt%-%)%& %R1,%0"
|
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[(set_attr "type" "fsqrt")
|
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(set_attr "trap" "yes")])
|
||||
|
|
@ -2326,7 +2334,7 @@
|
|||
(define_insn "sqrtdf2"
|
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[(set (match_operand:DF 0 "register_operand" "=f")
|
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(sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
|
||||
"TARGET_FP && TARGET_CIX"
|
||||
"TARGET_FP && TARGET_FIX"
|
||||
"sqrt%-%)%& %1,%0"
|
||||
[(set_attr "type" "fsqrt")
|
||||
(set_attr "trap" "yes")])
|
||||
|
|
@ -4015,7 +4023,7 @@
|
|||
(define_insn ""
|
||||
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,r,r,m,m")
|
||||
(match_operand:SF 1 "input_operand" "fG,m,rG,m,fG,r"))]
|
||||
"! TARGET_CIX
|
||||
"! TARGET_FIX
|
||||
&& (register_operand (operands[0], SFmode)
|
||||
|| reg_or_fp0_operand (operands[1], SFmode))"
|
||||
"@
|
||||
|
|
@ -4030,7 +4038,7 @@
|
|||
(define_insn ""
|
||||
[(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,r,r,m,m,f,*r")
|
||||
(match_operand:SF 1 "input_operand" "fG,m,rG,m,fG,r,r,*f"))]
|
||||
"TARGET_CIX
|
||||
"TARGET_FIX
|
||||
&& (register_operand (operands[0], SFmode)
|
||||
|| reg_or_fp0_operand (operands[1], SFmode))"
|
||||
"@
|
||||
|
|
@ -4047,7 +4055,7 @@
|
|||
(define_insn ""
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,r,r,m,m")
|
||||
(match_operand:DF 1 "input_operand" "fG,m,rG,m,fG,r"))]
|
||||
"! TARGET_CIX
|
||||
"! TARGET_FIX
|
||||
&& (register_operand (operands[0], DFmode)
|
||||
|| reg_or_fp0_operand (operands[1], DFmode))"
|
||||
"@
|
||||
|
|
@ -4062,7 +4070,7 @@
|
|||
(define_insn ""
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,r,r,m,m,f,*r")
|
||||
(match_operand:DF 1 "input_operand" "fG,m,rG,m,fG,r,r,*f"))]
|
||||
"TARGET_CIX
|
||||
"TARGET_FIX
|
||||
&& (register_operand (operands[0], DFmode)
|
||||
|| reg_or_fp0_operand (operands[1], DFmode))"
|
||||
"@
|
||||
|
|
@ -4101,7 +4109,7 @@
|
|||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m")
|
||||
(match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f"))]
|
||||
"! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_CIX
|
||||
"! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_FIX
|
||||
&& (register_operand (operands[0], SImode)
|
||||
|| reg_or_0_operand (operands[1], SImode))"
|
||||
"@
|
||||
|
|
@ -4118,7 +4126,7 @@
|
|||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m,r,*f")
|
||||
(match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f,f,*r"))]
|
||||
"! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_CIX
|
||||
"! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_FIX
|
||||
&& (register_operand (operands[0], SImode)
|
||||
|| reg_or_0_operand (operands[1], SImode))"
|
||||
"@
|
||||
|
|
@ -4250,7 +4258,7 @@
|
|||
(define_insn ""
|
||||
[(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,f,f,Q")
|
||||
(match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f"))]
|
||||
"! TARGET_CIX
|
||||
"! TARGET_FIX
|
||||
&& (register_operand (operands[0], DImode)
|
||||
|| reg_or_0_operand (operands[1], DImode))"
|
||||
"@
|
||||
|
|
@ -4268,7 +4276,7 @@
|
|||
(define_insn ""
|
||||
[(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,f,f,Q,r,*f")
|
||||
(match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f,f,*r"))]
|
||||
"TARGET_CIX
|
||||
"TARGET_FIX
|
||||
&& (register_operand (operands[0], DImode)
|
||||
|| reg_or_0_operand (operands[1], DImode))"
|
||||
"@
|
||||
|
|
@ -5307,5 +5315,5 @@
|
|||
; (match_operand:SI 1 "hard_fp_register_operand" "f"))
|
||||
; (set (match_operand:DI 2 "register_operand" "=r")
|
||||
; (sign_extend:DI (match_dup 0)))]
|
||||
; "TARGET_CIX && dead_or_set_p (insn, operands[0])"
|
||||
; "TARGET_FIX && dead_or_set_p (insn, operands[0])"
|
||||
; "ftois %1,%2")
|
||||
|
|
|
|||
|
|
@ -58,7 +58,7 @@ do { \
|
|||
} \
|
||||
fprintf (FILE, "\t.set noat\n"); \
|
||||
fprintf (FILE, "\t.set noreorder\n"); \
|
||||
if (TARGET_BWX | TARGET_MAX | TARGET_CIX) \
|
||||
if (TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX) \
|
||||
{ \
|
||||
fprintf (FILE, "\t.arch %s\n", \
|
||||
(alpha_cpu == PROCESSOR_EV6 ? "ev6" \
|
||||
|
|
|
|||
|
|
@ -5635,7 +5635,7 @@ for machine in $build $host $target; do
|
|||
alpha*-*-*)
|
||||
case $machine in
|
||||
alphaev6*)
|
||||
target_cpu_default2="MASK_CPU_EV6|MASK_BWX|MASK_CIX|MASK_MAX"
|
||||
target_cpu_default2="MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX"
|
||||
;;
|
||||
alphapca56*)
|
||||
target_cpu_default2="MASK_CPU_EV5|MASK_BWX|MASK_MAX"
|
||||
|
|
|
|||
|
|
@ -3332,7 +3332,7 @@ changequote([,])dnl
|
|||
alpha*-*-*)
|
||||
case $machine in
|
||||
alphaev6*)
|
||||
target_cpu_default2="MASK_CPU_EV6|MASK_BWX|MASK_CIX|MASK_MAX"
|
||||
target_cpu_default2="MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX"
|
||||
;;
|
||||
alphapca56*)
|
||||
target_cpu_default2="MASK_CPU_EV5|MASK_BWX|MASK_MAX"
|
||||
|
|
|
|||
Loading…
Reference in New Issue