m68hc11.c (m68hc11_addr_mode): New variable.
* config/m68hc11/m68hc11.c (m68hc11_addr_mode): New variable. (m68hc11_mov_addr_mode): Likewise. (m68hc11_override_options): Initialize them based on target. (register_indirect_p): Allow a MEM for indirect addressing modes and use flags to control what is allowed. (m68hc11_small_indexed_indirect_p): Use m68hc11_mov_addr_mode for supported addressing modes. (m68hc11_register_indirect_p): Use m68hc11_addr_mode. (go_if_legitimate_address_internal): Likewise. (m68hc11_indirect_p): Likewise and check the mode. (print_operand): Allow a (MEM (MEM)) and generate indirect addressing. From-SVN: r78792
This commit is contained in:
Stephane Carrez
Stephane Carrez
parent
d6da68b9d4
commit
de70723b1d
@ -1,3 +1,17 @@
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2004-03-02 Stephane Carrez <stcarrez@nerim.fr>
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* config/m68hc11/m68hc11.c (m68hc11_addr_mode): New variable.
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(m68hc11_mov_addr_mode): Likewise.
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(m68hc11_override_options): Initialize them based on target.
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(register_indirect_p): Allow a MEM for indirect addressing modes and
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use flags to control what is allowed.
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(m68hc11_small_indexed_indirect_p): Use m68hc11_mov_addr_mode for
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supported addressing modes.
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(m68hc11_register_indirect_p): Use m68hc11_addr_mode.
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(go_if_legitimate_address_internal): Likewise.
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(m68hc11_indirect_p): Likewise and check the mode.
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(print_operand): Allow a (MEM (MEM)) and generate indirect addressing.
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2004-03-02 Kazu Hirata <kazu@cs.umass.edu>
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* builtins.c (BUILTIN_SETJMP_FRAME_VALUE): Remove.
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@ -139,6 +139,16 @@ unsigned char m68hc11_reg_valid_for_index[FIRST_PSEUDO_REGISTER];
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This is 1 for 68HC11 and 0 for 68HC12. */
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int m68hc11_sp_correction;
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#define ADDR_STRICT 0x01 /* Accept only registers in class A_REGS */
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#define ADDR_INCDEC 0x02 /* Post/Pre inc/dec */
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#define ADDR_INDEXED 0x04 /* D-reg index */
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#define ADDR_OFFSET 0x08
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#define ADDR_INDIRECT 0x10 /* Accept (mem (mem ...)) for [n,X] */
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#define ADDR_CONST 0x20 /* Accept const and symbol_ref */
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int m68hc11_addr_mode;
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int m68hc11_mov_addr_mode;
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/* Comparison operands saved by the "tstxx" and "cmpxx" expand patterns. */
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rtx m68hc11_compare_op0;
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rtx m68hc11_compare_op1;
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@ -298,6 +308,8 @@ m68hc11_override_options (void)
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m68hc11_reg_valid_for_base[HARD_Z_REGNUM] = 1;
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m68hc11_sp_correction = 1;
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m68hc11_tmp_regs_class = D_REGS;
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m68hc11_addr_mode = ADDR_OFFSET;
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m68hc11_mov_addr_mode = 0;
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if (m68hc11_soft_reg_count == 0 && !TARGET_M6812)
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m68hc11_soft_reg_count = "4";
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}
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@ -317,6 +329,10 @@ m68hc11_override_options (void)
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m68hc11_reg_valid_for_index[HARD_D_REGNUM] = 1;
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m68hc11_sp_correction = 0;
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m68hc11_tmp_regs_class = TMP_REGS;
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m68hc11_addr_mode = ADDR_INDIRECT | ADDR_OFFSET | ADDR_CONST
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| (TARGET_AUTO_INC_DEC ? ADDR_INCDEC : 0);
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m68hc11_mov_addr_mode = ADDR_OFFSET | ADDR_CONST
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| (TARGET_AUTO_INC_DEC ? ADDR_INCDEC : 0);
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target_flags &= ~MASK_M6811;
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target_flags |= MASK_NO_DIRECT_MODE;
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if (m68hc11_soft_reg_count == 0)
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@ -551,18 +567,25 @@ preferred_reload_class (rtx operand, enum reg_class class)
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For 68hc11: n,r with n in [0..255] and r in A_REGS class
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For 68hc12: n,r no constraint on the constant, r in A_REGS class. */
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static int
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register_indirect_p (rtx operand, enum machine_mode mode, int strict)
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register_indirect_p (rtx operand, enum machine_mode mode, int addr_mode)
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{
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rtx base, offset;
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switch (GET_CODE (operand))
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{
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case MEM:
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if ((addr_mode & ADDR_INDIRECT) && GET_MODE_SIZE (mode) <= 2)
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return register_indirect_p (XEXP (operand, 0), mode,
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addr_mode & (ADDR_STRICT | ADDR_OFFSET));
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return 0;
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case POST_INC:
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case PRE_INC:
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case POST_DEC:
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case PRE_DEC:
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if (TARGET_M6812 && TARGET_AUTO_INC_DEC)
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return register_indirect_p (XEXP (operand, 0), mode, strict);
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if (addr_mode & ADDR_INCDEC)
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return register_indirect_p (XEXP (operand, 0), mode,
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addr_mode & ADDR_STRICT);
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return 0;
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case PLUS:
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@ -574,36 +597,57 @@ register_indirect_p (rtx operand, enum machine_mode mode, int strict)
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if (GET_CODE (offset) == MEM)
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return 0;
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/* Indexed addressing mode with 2 registers. */
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if (GET_CODE (base) == REG && GET_CODE (offset) == REG)
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{
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if (!(addr_mode & ADDR_INDEXED))
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return 0;
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addr_mode &= ADDR_STRICT;
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if (REGNO_OK_FOR_BASE_P2 (REGNO (base), addr_mode)
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&& REGNO_OK_FOR_INDEX_P2 (REGNO (offset), addr_mode))
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return 1;
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if (REGNO_OK_FOR_BASE_P2 (REGNO (offset), addr_mode)
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&& REGNO_OK_FOR_INDEX_P2 (REGNO (base), addr_mode))
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return 1;
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return 0;
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}
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if (!(addr_mode & ADDR_OFFSET))
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return 0;
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if (GET_CODE (base) == REG)
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{
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if (!VALID_CONSTANT_OFFSET_P (offset, mode))
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if (!VALID_CONSTANT_OFFSET_P (offset, mode))
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return 0;
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if (strict == 0)
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if (!(addr_mode & ADDR_STRICT))
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return 1;
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return REGNO_OK_FOR_BASE_P2 (REGNO (base), strict);
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return REGNO_OK_FOR_BASE_P2 (REGNO (base), 1);
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}
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if (GET_CODE (offset) == REG)
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{
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if (!VALID_CONSTANT_OFFSET_P (base, mode))
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return 0;
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if (strict == 0)
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if (!(addr_mode & ADDR_STRICT))
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return 1;
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return REGNO_OK_FOR_BASE_P2 (REGNO (offset), strict);
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return REGNO_OK_FOR_BASE_P2 (REGNO (offset), 1);
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}
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return 0;
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case REG:
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return REGNO_OK_FOR_BASE_P2 (REGNO (operand), strict);
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return REGNO_OK_FOR_BASE_P2 (REGNO (operand), addr_mode & ADDR_STRICT);
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case CONST_INT:
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if (TARGET_M6811)
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return 0;
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return VALID_CONSTANT_OFFSET_P (operand, mode);
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if (addr_mode & ADDR_CONST)
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return VALID_CONSTANT_OFFSET_P (operand, mode);
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return 0;
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default:
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return 0;
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@ -616,6 +660,7 @@ int
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m68hc11_small_indexed_indirect_p (rtx operand, enum machine_mode mode)
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{
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rtx base, offset;
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int addr_mode;
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if (GET_CODE (operand) == REG && reload_in_progress
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&& REGNO (operand) >= FIRST_PSEUDO_REGISTER
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@ -635,7 +680,8 @@ m68hc11_small_indexed_indirect_p (rtx operand, enum machine_mode mode)
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if (PUSH_POP_ADDRESS_P (operand))
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return 1;
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if (!register_indirect_p (operand, mode, reload_completed))
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addr_mode = m68hc11_mov_addr_mode | (reload_completed ? ADDR_STRICT : 0);
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if (!register_indirect_p (operand, mode, addr_mode))
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return 0;
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if (TARGET_M6812 && GET_CODE (operand) == PLUS
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@ -676,18 +722,29 @@ m68hc11_small_indexed_indirect_p (rtx operand, enum machine_mode mode)
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int
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m68hc11_register_indirect_p (rtx operand, enum machine_mode mode)
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{
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int addr_mode;
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if (GET_CODE (operand) == REG && reload_in_progress
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&& REGNO (operand) >= FIRST_PSEUDO_REGISTER
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&& reg_equiv_memory_loc[REGNO (operand)])
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{
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operand = reg_equiv_memory_loc[REGNO (operand)];
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operand = eliminate_regs (operand, 0, NULL_RTX);
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}
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if (GET_CODE (operand) != MEM)
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return 0;
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operand = XEXP (operand, 0);
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return register_indirect_p (operand, mode,
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(reload_completed | reload_in_progress));
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addr_mode = m68hc11_addr_mode | (reload_completed ? ADDR_STRICT : 0);
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return register_indirect_p (operand, mode, addr_mode);
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}
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static int
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go_if_legitimate_address_internal (rtx operand, enum machine_mode mode,
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int strict)
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{
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int addr_mode;
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if (CONSTANT_ADDRESS_P (operand) && TARGET_M6812)
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{
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/* Reject the global variables if they are too wide. This forces
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@ -697,7 +754,8 @@ go_if_legitimate_address_internal (rtx operand, enum machine_mode mode,
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return 1;
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}
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if (register_indirect_p (operand, mode, strict))
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addr_mode = m68hc11_addr_mode | (strict ? ADDR_STRICT : 0);
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if (register_indirect_p (operand, mode, addr_mode))
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{
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return 1;
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}
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@ -984,18 +1042,20 @@ m68hc11_symbolic_p (rtx operand, enum machine_mode mode)
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int
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m68hc11_indirect_p (rtx operand, enum machine_mode mode)
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{
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if (GET_CODE (operand) == MEM)
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if (GET_CODE (operand) == MEM && GET_MODE (operand) == mode)
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{
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rtx op = XEXP (operand, 0);
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int addr_mode;
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if (symbolic_memory_operand (op, mode))
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return 0;
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return TARGET_M6812;
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if (reload_in_progress)
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return 1;
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operand = XEXP (operand, 0);
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return register_indirect_p (operand, mode, reload_completed);
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addr_mode = m68hc11_addr_mode | (reload_completed ? ADDR_STRICT : 0);
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return register_indirect_p (operand, mode, addr_mode);
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}
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return 0;
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}
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@ -2247,7 +2307,21 @@ print_operand (FILE *file, rtx op, int letter)
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abort ();
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break;
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case MEM:
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if (TARGET_M6812)
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{
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fprintf (file, "[");
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print_operand_address (file, XEXP (base, 0));
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fprintf (file, "]");
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}
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else
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abort ();
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break;
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default:
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if (m68hc11_page0_symbol_p (base))
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fprintf (file, "*");
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output_address (base);
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break;
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}
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