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re PR c++/38256 (ICE with "operator auto")

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PR target/38256
	* config/i386/sync.md (memory_barrier_nosse): New insn
	(memory_barrier): Generate memory_barrier_nosse insn for !TARGET_SSE2.

From-SVN: r142177
This commit is contained in:
Uros Bizjak 2008-11-25 01:12:15 +01:00 committed by Uros Bizjak
parent 467a1bf1e9
commit decc2ec39a
2 changed files with 26 additions and 9 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2008-11-25 Uros Bizjak <ubizjak@gmail.com>
PR target/38256
* config/i386/sync.md (memory_barrier_nosse): New insn
(memory_barrier): Generate memory_barrier_nosse insn for !TARGET_SSE2.
2008-11-24 Maxim Kuvyrkov <maxim@codesourcery.com> 2008-11-24 Maxim Kuvyrkov <maxim@codesourcery.com>
* config/m68k/m68k.md (cmpdi): Use (scratch) instead of pseudo. * config/m68k/m68k.md (cmpdi): Use (scratch) instead of pseudo.

29
gcc/config/i386/sync.md
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@ -36,19 +36,30 @@
(unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))] (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
"" ""
{ {
if (!TARGET_SSE2)
{
/* Emit a locked no-operation when SSE2 is not available. */
int slot = virtuals_instantiated ? SLOT_TEMP : SLOT_VIRTUAL;
rtx temp = assign_386_stack_local (QImode, slot);
emit_insn (gen_sync_iorqi (temp, CONST0_RTX (QImode)));
DONE;
}
operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
MEM_VOLATILE_P (operands[0]) = 1; MEM_VOLATILE_P (operands[0]) = 1;
if (!TARGET_SSE2)
{
emit_insn (gen_memory_barrier_nosse (operands[0]));
DONE;
}
}) })
(define_insn "memory_barrier_nosse"
[(set (match_operand:BLK 0 "" "")
(unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_SSE2"
{
if (TARGET_64BIT)
return "lock{%;| }or{q}\t{$0, (%%rsp)|QWORD PTR [rsp], 0}";
else
return "lock{%;| }or{l}\t{$0, (%%esp)|DWORD PTR [esp], 0}";
}
[(set_attr "memory" "unknown")])
;; ??? It would be possible to use cmpxchg8b on pentium for DImode ;; ??? It would be possible to use cmpxchg8b on pentium for DImode
;; changes. It's complicated because the insn uses ecx:ebx as the ;; changes. It's complicated because the insn uses ecx:ebx as the
;; new value; note that the registers are reversed from the order ;; new value; note that the registers are reversed from the order