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arm.opt (masm-syntax-unified): New option.

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gcc/ChangeLog:
2014-11-07  Terry Guo  <terry.guo@arm.com>

	* config/arm/arm.opt (masm-syntax-unified): New option.
	* doc/invoke.texi (-masm-syntax-unified): Document new option.
	* config/arm/arm.h (TARGET_UNIFIED_ASM): Also include thumb1.
	(ASM_APP_ON): Redefined.
	* config/arm/arm.c (arm_option_override): Thumb2 inline assembly
	code always use UAL syntax.
	(arm_output_mi_thunk): Use UAL syntax for Thumb1 target.
	* config/arm/thumb1.md: Likewise.

gcc/testsuite/ChangeLog:
2014-11-07  Terry Guo  <terry.guo@arm.com>

	* gcc.target/arm/anddi_notdi-1.c: Match with UAL format.
	* gcc.target/arm/pr40956.c: Likewise.
	* gcc.target/arm/thumb1-Os-mult.c: Likewise.
	* gcc.target/arm/thumb1-load-64bit-constant-3.c: Likewise.
	* gcc.target/arm/scd42-1.c: Likewise.

From-SVN: r217211
This commit is contained in:
Terry Guo 2014-11-07 03:02:29 +00:00 committed by Xuepeng Guo
parent efb1c0d318
commit decfc6e113
12 changed files with 111 additions and 61 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
gcc/ChangeLog
View File

@ -1,3 +1,14 @@
2014-11-07 Terry Guo <terry.guo@arm.com>
* config/arm/arm.opt (masm-syntax-unified): New option.
* doc/invoke.texi (-masm-syntax-unified): Document new option.
* config/arm/arm.h (TARGET_UNIFIED_ASM): Also include thumb1.
(ASM_APP_ON): Redefined.
* config/arm/arm.c (arm_option_override): Thumb2 inline assembly
code always use UAL syntax.
(arm_output_mi_thunk): Use UAL syntax for Thumb1 target.
* config/arm/thumb1.md: Likewise.
2014-11-06 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.md (trap): New insn. Add "trap" to attribute type.

11
gcc/config/arm/arm.c
View File

@ -3162,6 +3162,11 @@ arm_option_override (void)
if (target_slow_flash_data)
arm_disable_literal_pool = true;
/* Thumb2 inline assembly code should always use unified syntax.
This will apply to ARM and Thumb1 eventually. */
if (TARGET_THUMB2)
inline_asm_unified = 1;
/* Register global variables with the garbage collector. */
arm_add_gc_roots ();
}
@ -28658,12 +28663,14 @@ arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
fputs ("\tldr\tr3, ", file);
assemble_name (file, label);
fputs ("+4\n", file);
asm_fprintf (file, "\t%s\t%r, %r, r3\n",
asm_fprintf (file, "\t%ss\t%r, %r, r3\n",
mi_op, this_regno, this_regno);
}
else if (mi_delta != 0)
{
asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
/* Thumb1 unified syntax requires s suffix in instruction name when
one of the operands is immediate. */
asm_fprintf (file, "\t%ss\t%r, %r, #%d\n",
mi_op, this_regno, this_regno,
mi_delta);
}

13
gcc/config/arm/arm.h
View File

@ -168,6 +168,8 @@ extern char arm_arch_name[];
builtin_define ("__ARM_ARCH_EXT_IDIV__"); \
builtin_define ("__ARM_FEATURE_IDIV"); \
} \
if (inline_asm_unified) \
builtin_define ("__ARM_ASM_SYNTAX_UNIFIED__");\
} while (0)
#include "config/arm/arm-opts.h"
@ -351,8 +353,8 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
|| (!optimize_size && !current_tune->prefer_constant_pool)))
/* We could use unified syntax for arm mode, but for now we just use it
for Thumb-2. */
#define TARGET_UNIFIED_ASM TARGET_THUMB2
for thumb mode. */
#define TARGET_UNIFIED_ASM (TARGET_THUMB)
/* Nonzero if this chip provides the DMB instruction. */
#define TARGET_HAVE_DMB (arm_arch6m || arm_arch7)
@ -2150,8 +2152,13 @@ extern int making_const_table;
#define CC_STATUS_INIT \
do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0)
#undef ASM_APP_ON
#define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \
"\t.syntax divided\n")
#undef ASM_APP_OFF
#define ASM_APP_OFF (TARGET_ARM ? "" : "\t.thumb\n")
#define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax divided\n" : \
"\t.thumb\n\t.syntax unified\n")
/* Output a push or a pop instruction (only used when profiling).
We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know

4
gcc/config/arm/arm.opt
View File

@ -271,3 +271,7 @@ Use Neon to perform 64-bits operations rather than core registers.
mslow-flash-data
Target Report Var(target_slow_flash_data) Init(0)
Assume loading data from flash is slower than fetching instructions.
masm-syntax-unified
Target Report Var(inline_asm_unified) Init(0)
Assume unified syntax for Thumb inline assembly code.

102
gcc/config/arm/thumb1.md
View File

@ -29,7 +29,7 @@
(clobber (reg:CC CC_REGNUM))
]
"TARGET_THUMB1"
"add\\t%Q0, %Q0, %Q2\;adc\\t%R0, %R0, %R2"
"adds\\t%Q0, %Q0, %Q2\;adcs\\t%R0, %R0, %R2"
[(set_attr "length" "4")
(set_attr "type" "multiple")]
)
@ -42,9 +42,9 @@
"*
static const char * const asms[] =
{
\"add\\t%0, %0, %2\",
\"sub\\t%0, %0, #%n2\",
\"add\\t%0, %1, %2\",
\"adds\\t%0, %0, %2\",
\"subs\\t%0, %0, #%n2\",
\"adds\\t%0, %1, %2\",
\"add\\t%0, %0, %2\",
\"add\\t%0, %0, %2\",
\"add\\t%0, %1, %2\",
@ -56,7 +56,7 @@
if ((which_alternative == 2 || which_alternative == 6)
&& CONST_INT_P (operands[2])
&& INTVAL (operands[2]) < 0)
return \"sub\\t%0, %1, #%n2\";
return (which_alternative == 2) ? \"subs\\t%0, %1, #%n2\" : \"sub\\t%0, %1, #%n2\";
return asms[which_alternative];
"
"&& reload_completed && CONST_INT_P (operands[2])
@ -105,7 +105,7 @@
(match_operand:DI 2 "register_operand" "l")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB1"
"sub\\t%Q0, %Q0, %Q2\;sbc\\t%R0, %R0, %R2"
"subs\\t%Q0, %Q0, %Q2\;sbcs\\t%R0, %R0, %R2"
[(set_attr "length" "4")
(set_attr "type" "multiple")]
)
@ -115,7 +115,7 @@
(minus:SI (match_operand:SI 1 "register_operand" "l")
(match_operand:SI 2 "reg_or_int_operand" "lPd")))]
"TARGET_THUMB1"
"sub\\t%0, %1, %2"
"subs\\t%0, %1, %2"
[(set_attr "length" "2")
(set_attr "conds" "set")
(set_attr "type" "alus_sreg")]
@ -133,9 +133,9 @@
"TARGET_THUMB1 && !arm_arch6"
"*
if (which_alternative < 2)
return \"mov\\t%0, %1\;mul\\t%0, %2\";
return \"mov\\t%0, %1\;muls\\t%0, %2\";
else
return \"mul\\t%0, %2\";
return \"muls\\t%0, %2\";
"
[(set_attr "length" "4,4,2")
(set_attr "type" "muls")]
@ -147,9 +147,9 @@
(match_operand:SI 2 "register_operand" "l,0,0")))]
"TARGET_THUMB1 && arm_arch6"
"@
mul\\t%0, %2
mul\\t%0, %1
mul\\t%0, %1"
muls\\t%0, %2
muls\\t%0, %1
muls\\t%0, %1"
[(set_attr "length" "2")
(set_attr "type" "muls")]
)
@ -159,7 +159,7 @@
(and:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "register_operand" "l")))]
"TARGET_THUMB1"
"and\\t%0, %2"
"ands\\t%0, %2"
[(set_attr "length" "2")
(set_attr "type" "logic_imm")
(set_attr "conds" "set")])
@ -202,7 +202,7 @@
(and:SI (not:SI (match_operand:SI 1 "register_operand" "l"))
(match_operand:SI 2 "register_operand" "0")))]
"TARGET_THUMB1"
"bic\\t%0, %1"
"bics\\t%0, %1"
[(set_attr "length" "2")
(set_attr "conds" "set")
(set_attr "type" "logics_reg")]
@ -213,7 +213,7 @@
(ior:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "register_operand" "l")))]
"TARGET_THUMB1"
"orr\\t%0, %2"
"orrs\\t%0, %2"
[(set_attr "length" "2")
(set_attr "conds" "set")
(set_attr "type" "logics_reg")])
@ -223,7 +223,7 @@
(xor:SI (match_operand:SI 1 "register_operand" "%0")
(match_operand:SI 2 "register_operand" "l")))]
"TARGET_THUMB1"
"eor\\t%0, %2"
"eors\\t%0, %2"
[(set_attr "length" "2")
(set_attr "conds" "set")
(set_attr "type" "logics_reg")]
@ -234,7 +234,7 @@
(ashift:SI (match_operand:SI 1 "register_operand" "l,0")
(match_operand:SI 2 "nonmemory_operand" "N,l")))]
"TARGET_THUMB1"
"lsl\\t%0, %1, %2"
"lsls\\t%0, %1, %2"
[(set_attr "length" "2")
(set_attr "type" "shift_imm,shift_reg")
(set_attr "conds" "set")])
@ -244,7 +244,7 @@
(ashiftrt:SI (match_operand:SI 1 "register_operand" "l,0")
(match_operand:SI 2 "nonmemory_operand" "N,l")))]
"TARGET_THUMB1"
"asr\\t%0, %1, %2"
"asrs\\t%0, %1, %2"
[(set_attr "length" "2")
(set_attr "type" "shift_imm,shift_reg")
(set_attr "conds" "set")])
@ -254,7 +254,7 @@
(lshiftrt:SI (match_operand:SI 1 "register_operand" "l,0")
(match_operand:SI 2 "nonmemory_operand" "N,l")))]
"TARGET_THUMB1"
"lsr\\t%0, %1, %2"
"lsrs\\t%0, %1, %2"
[(set_attr "length" "2")
(set_attr "type" "shift_imm,shift_reg")
(set_attr "conds" "set")])
@ -264,7 +264,7 @@
(rotatert:SI (match_operand:SI 1 "register_operand" "0")
(match_operand:SI 2 "register_operand" "l")))]
"TARGET_THUMB1"
"ror\\t%0, %0, %2"
"rors\\t%0, %0, %2"
[(set_attr "type" "shift_reg")
(set_attr "length" "2")]
)
@ -274,7 +274,7 @@
(neg:DI (match_operand:DI 1 "register_operand" "l")))
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB1"
"mov\\t%R0, #0\;neg\\t%Q0, %Q1\;sbc\\t%R0, %R1"
"movs\\t%R0, #0\;rsbs\\t%Q0, %Q1, #0\;sbcs\\t%R0, %R1"
[(set_attr "length" "6")
(set_attr "type" "multiple")]
)
@ -283,7 +283,7 @@
[(set (match_operand:SI 0 "register_operand" "=l")
(neg:SI (match_operand:SI 1 "register_operand" "l")))]
"TARGET_THUMB1"
"neg\\t%0, %1"
"rsbs\\t%0, %1, #0"
[(set_attr "length" "2")
(set_attr "type" "alu_imm")]
)
@ -322,7 +322,7 @@
[(set (match_operand:SI 0 "register_operand" "=l")
(not:SI (match_operand:SI 1 "register_operand" "l")))]
"TARGET_THUMB1"
"mvn\\t%0, %1"
"mvns\\t%0, %1"
[(set_attr "length" "2")
(set_attr "type" "mvn_reg")]
)
@ -456,7 +456,7 @@
ops[3] = ops[0];
else
ops[3] = operands[2];
output_asm_insn (\"mov\\t%3, %2\;ldrsh\\t%0, [%1, %3]\", ops);
output_asm_insn (\"movs\\t%3, %2\;ldrsh\\t%0, [%1, %3]\", ops);
return \"\";
}"
[(set_attr_alternative "length"
@ -586,10 +586,10 @@
return \"add\\t%0, %1, #0\;add\\t%H0, %H1, #0\";
return \"add\\t%H0, %H1, #0\;add\\t%0, %1, #0\";
case 1:
return \"mov\\t%Q0, %1\;mov\\t%R0, #0\";
return \"movs\\t%Q0, %1\;movs\\t%R0, #0\";
case 2:
operands[1] = GEN_INT (- INTVAL (operands[1]));
return \"mov\\t%Q0, %1\;neg\\t%Q0, %Q0\;asr\\t%R0, %Q0, #31\";
return \"movs\\t%Q0, %1\;rsbs\\t%Q0, %Q0, #0\;asrs\\t%R0, %Q0, #31\";
case 3:
return \"ldmia\\t%1, {%0, %H0}\";
case 4:
@ -619,8 +619,8 @@
&& ( register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode))"
"@
mov %0, %1
mov %0, %1
movs %0, %1
movs %0, %1
#
#
ldmia\\t%1, {%0}
@ -715,11 +715,11 @@
"*
switch (which_alternative)
{
case 0: return \"add %0, %1, #0\";
case 0: return \"adds %0, %1, #0\";
case 2: return \"strh %1, %0\";
case 3: return \"mov %0, %1\";
case 4: return \"mov %0, %1\";
case 5: return \"mov %0, %1\";
case 5: return \"movs %0, %1\";
default: gcc_unreachable ();
case 1:
/* The stack pointer can end up being taken as an index register.
@ -767,12 +767,12 @@
&& ( register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode))"
"@
add\\t%0, %1, #0
adds\\t%0, %1, #0
ldrb\\t%0, %1
strb\\t%1, %0
mov\\t%0, %1
mov\\t%0, %1
mov\\t%0, %1"
movs\\t%0, %1"
[(set_attr "length" "2")
(set_attr "type" "alu_imm,load1,store1,mov_reg,mov_imm,mov_imm")
(set_attr "pool_range" "*,32,*,*,*,*")
@ -819,7 +819,7 @@
&& ( register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))"
"@
add\\t%0, %1, #0
adds\\t%0, %1, #0
ldmia\\t%1, {%0}
stmia\\t%0, {%1}
ldr\\t%0, %1
@ -848,8 +848,8 @@
default:
case 0:
if (REGNO (operands[1]) == REGNO (operands[0]) + 1)
return \"add\\t%0, %1, #0\;add\\t%H0, %H1, #0\";
return \"add\\t%H0, %H1, #0\;add\\t%0, %1, #0\";
return \"adds\\t%0, %1, #0\;adds\\t%H0, %H1, #0\";
return \"adds\\t%H0, %H1, #0\;adds\\t%0, %1, #0\";
case 1:
return \"ldmia\\t%1, {%0, %H0}\";
case 2:
@ -1013,7 +1013,7 @@
(clobber (match_scratch:SI 0 "=l,l"))]
"TARGET_THUMB1"
"*
output_asm_insn (\"add\\t%0, %1, #%n2\", operands);
output_asm_insn (\"adds\\t%0, %1, #%n2\", operands);
switch (get_attr_length (insn))
{
@ -1095,7 +1095,7 @@
op[1] = operands[1];
op[2] = GEN_INT (32 - 1 - INTVAL (operands[2]));
output_asm_insn (\"lsl\\t%0, %1, %2\", op);
output_asm_insn (\"lsls\\t%0, %1, %2\", op);
switch (get_attr_length (insn))
{
case 4: return \"b%d0\\t%l3\";
@ -1140,7 +1140,7 @@
op[1] = operands[1];
op[2] = GEN_INT (32 - INTVAL (operands[2]));
output_asm_insn (\"lsl\\t%0, %1, %2\", op);
output_asm_insn (\"lsls\\t%0, %1, %2\", op);
switch (get_attr_length (insn))
{
case 4: return \"b%d0\\t%l3\";
@ -1224,20 +1224,20 @@
cond[1] = operands[4];
if (which_alternative == 0)
output_asm_insn (\"sub\\t%0, %2, #1\", operands);
output_asm_insn (\"subs\\t%0, %2, #1\", operands);
else if (which_alternative == 1)
{
/* We must provide an alternative for a hi reg because reload
cannot handle output reloads on a jump instruction, but we
can't subtract into that. Fortunately a mov from lo to hi
does not clobber the condition codes. */
output_asm_insn (\"sub\\t%1, %2, #1\", operands);
output_asm_insn (\"subs\\t%1, %2, #1\", operands);
output_asm_insn (\"mov\\t%0, %1\", operands);
}
else
{
/* Similarly, but the target is memory. */
output_asm_insn (\"sub\\t%1, %2, #1\", operands);
output_asm_insn (\"subs\\t%1, %2, #1\", operands);
output_asm_insn (\"str\\t%1, %0\", operands);
}
@ -1336,9 +1336,9 @@
cond[2] = operands[3];
if (CONST_INT_P (cond[2]) && INTVAL (cond[2]) < 0)
output_asm_insn (\"sub\\t%0, %1, #%n2\", cond);
output_asm_insn (\"subs\\t%0, %1, #%n2\", cond);
else
output_asm_insn (\"add\\t%0, %1, %2\", cond);
output_asm_insn (\"adds\\t%0, %1, %2\", cond);
if (which_alternative >= 2
&& which_alternative < 4)
@ -1418,13 +1418,13 @@
break;
case 2:
if (INTVAL (operands[2]) < 0)
output_asm_insn (\"sub\t%0, %1, %2\", operands);
output_asm_insn (\"subs\t%0, %1, %2\", operands);
else
output_asm_insn (\"add\t%0, %1, %2\", operands);
break;
case 3:
if (INTVAL (operands[2]) < 0)
output_asm_insn (\"sub\t%0, %0, %2\", operands);
output_asm_insn (\"subs\t%0, %0, %2\", operands);
else
output_asm_insn (\"add\t%0, %0, %2\", operands);
break;
@ -1465,7 +1465,7 @@
(const_int 0)))
(clobber (match_scratch:SI 1 "=l"))]
"TARGET_THUMB1"
"orr\\t%1, %Q0, %R0"
"orrs\\t%1, %Q0, %R0"
[(set_attr "conds" "set")
(set_attr "length" "2")
(set_attr "type" "logics_reg")]
@ -1498,8 +1498,8 @@
(clobber (match_operand:SI 2 "s_register_operand" "=X,l"))]
"TARGET_THUMB1"
"@
neg\\t%0, %1\;adc\\t%0, %0, %1
neg\\t%2, %1\;adc\\t%0, %1, %2"
rsbs\\t%0, %1, #0\;adcs\\t%0, %0, %1
rsbs\\t%2, %1, #0\;adcs\\t%0, %1, %2"
[(set_attr "length" "4")
(set_attr "type" "multiple")]
)
@ -1510,7 +1510,7 @@
(const_int 0)))
(clobber (match_operand:SI 2 "s_register_operand" "=l"))]
"TARGET_THUMB1"
"sub\\t%2, %1, #1\;sbc\\t%0, %1, %2"
"subs\\t%2, %1, #1\;sbcs\\t%0, %1, %2"
[(set_attr "length" "4")]
)
@ -1520,7 +1520,7 @@
(neg:SI (ltu:SI (match_operand:SI 1 "s_register_operand" "l,*h")
(match_operand:SI 2 "thumb1_cmp_operand" "lI*h,*r"))))]
"TARGET_THUMB1"
"cmp\\t%1, %2\;sbc\\t%0, %0, %0"
"cmp\\t%1, %2\;sbcs\\t%0, %0, %0"
[(set_attr "length" "4")
(set_attr "type" "multiple")]
)
@ -1548,7 +1548,7 @@
(geu:SI (match_operand:SI 3 "s_register_operand" "l")
(match_operand:SI 4 "thumb1_cmp_operand" "lI"))))]
"TARGET_THUMB1"
"cmp\\t%3, %4\;adc\\t%0, %1, %2"
"cmp\\t%3, %4\;adcs\\t%0, %1, %2"
[(set_attr "length" "4")
(set_attr "type" "multiple")]
)

11
gcc/doc/invoke.texi
View File

@ -546,6 +546,7 @@ Objective-C and Objective-C++ Dialects}.
-munaligned-access @gol
-mneon-for-64bits @gol
-mslow-flash-data @gol
-masm-syntax-unified @gol
-mrestrict-it}
@emph{AVR Options}
@ -13026,6 +13027,16 @@ Therefore literal load is minimized for better performance.
This option is only supported when compiling for ARMv7 M-profile and
off by default.
@item -masm-syntax-unified
@opindex masm-syntax-unified
Assume the Thumb1 inline assembly code are using unified syntax.
The default is currently off, which means divided syntax is assumed.
However, this may change in future releases of GCC. Divided syntax
should be considered deprecated. This option has no effect when
generating Thumb2 code. Thumb2 assembly code always uses unified syntax.
This option has no effect for ARM state assembly code which will still
uses divided syntax.
@item -mrestrict-it
@opindex mrestrict-it
Restricts generation of IT blocks to conform to the rules of ARMv8.

8
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,11 @@
2014-11-07 Terry Guo <terry.guo@arm.com>
* gcc.target/arm/anddi_notdi-1.c: Match with UAL format.
* gcc.target/arm/pr40956.c: Likewise.
* gcc.target/arm/thumb1-Os-mult.c: Likewise.
* gcc.target/arm/thumb1-load-64bit-constant-3.c: Likewise.
* gcc.target/arm/scd42-1.c: Likewise.
2014-11-06 Joseph Myers <joseph@codesourcery.com>
* g++.dg/cpp/ucnid-2.C, g++.dg/cpp/ucnid-3.C,

3
gcc/testsuite/gcc.target/arm/anddi_notdi-1.c
View File

@ -60,6 +60,7 @@ int main ()
return 0;
}
/* { dg-final { scan-assembler-times "bic\t" 6 } } */
/* { dg-final { scan-assembler-times "bics\t" 6 { target arm_thumb1 } } } */
/* { dg-final { scan-assembler-times "bic\t" 6 { target { ! arm_thumb1 } } } } */
/* { dg-final { cleanup-saved-temps } } */

3
gcc/testsuite/gcc.target/arm/pr40956.c
View File

@ -1,7 +1,8 @@
/* { dg-options "-Os -fpic" } */
/* { dg-require-effective-target fpic } */
/* Make sure the constant "0" is loaded into register only once. */
/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 } } */
/* { dg-final { scan-assembler-times "movs\[\\t \]*r., #0" 1 { target arm_thumb1 } } } */
/* { dg-final { scan-assembler-times "mov\[\\t \]*r., #0" 1 { target { ! arm_thumb1 } } } } */
int foo(int p, int* q)
{

2
gcc/testsuite/gcc.target/arm/scd42-1.c
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@ -13,4 +13,4 @@ unsigned load1(void)
return 17;
}
/* { dg-final { scan-assembler "mov\[ ].*17" } } */
/* { dg-final { scan-assembler "movs\[ ].*17" } } */

2
gcc/testsuite/gcc.target/arm/thumb1-Os-mult.c
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@ -9,4 +9,4 @@ mymul3 (int x)
return x * 0x555;
}
/* { dg-final { scan-assembler "mul\[\\t \]*r.,\[\\t \]*r." } } */
/* { dg-final { scan-assembler "muls\[\\t \]*r.,\[\\t \]*r." } } */

2
gcc/testsuite/gcc.target/arm/thumb1-load-64bit-constant-3.c
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@ -10,5 +10,5 @@ foo (int len)
}
/* { dg-final { scan-assembler-not "ldr" } } */
/* { dg-final { scan-assembler-times "neg" 1 } } */
/* { dg-final { scan-assembler-times "rsbs" 1 } } */