From e00199d7b78ccff66112b17b8c9bb07f67f40e66 Mon Sep 17 00:00:00 2001 From: Jakub Jelinek Date: Thu, 13 Dec 2018 09:00:42 +0100 Subject: [PATCH] re PR target/88461 (AVX512: gcc should keep value in kN registers if possible) PR target/88461 * config/i386/sse.md (VI1248_AVX512VLBW, AVX512ZEXTMASK): New mode iterators. (_testm3, _testnm3): Merge patterns with VI12_AVX512VL and VI48_AVX512VL iterators into ones with VI1248_AVX512VLBW iterator. (*_testm3_zext, *_testm3_zext_mask, *_testnm3_zext, *_testnm3_zext_mask): New define_insns. * gcc.target/i386/pr88461.c: New test. From-SVN: r267077 --- gcc/ChangeLog | 13 ++++ gcc/config/i386/sse.md | 99 ++++++++++++++++++------- gcc/testsuite/ChangeLog | 5 ++ gcc/testsuite/gcc.target/i386/pr88461.c | 16 ++++ 4 files changed, 108 insertions(+), 25 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr88461.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4e96dd061ca..55c291b8e59 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,18 @@ 2018-12-13 Jakub Jelinek + PR target/88461 + * config/i386/sse.md (VI1248_AVX512VLBW, AVX512ZEXTMASK): New + mode iterators. + (_testm3, + _testnm3): Merge patterns + with VI12_AVX512VL and VI48_AVX512VL iterators into ones with + VI1248_AVX512VLBW iterator. + (*_testm3_zext, + *_testm3_zext_mask, + *_testnm3_zext, + *_testnm3_zext_mask): New + define_insns. + PR target/88461 * config/i386/i386.md (*zero_extendsidi2, zero_extenddi2, *zero_extendsi2, *zero_extendqihi2): Add =*k, *km alternatives. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 52db04dda97..be65f902d9e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -12322,22 +12322,22 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "_testm3" - [(set (match_operand: 0 "register_operand" "=Yk") - (unspec: - [(match_operand:VI12_AVX512VL 1 "register_operand" "v") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")] - UNSPEC_TESTM))] - "TARGET_AVX512BW" - "vptestm\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "prefix" "evex") - (set_attr "mode" "")]) +(define_mode_iterator VI1248_AVX512VLBW + [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX512VL && TARGET_AVX512BW") + (V16QI "TARGET_AVX512VL && TARGET_AVX512BW") + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX512VL && TARGET_AVX512BW") + (V8HI "TARGET_AVX512VL && TARGET_AVX512BW") + V16SI (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL") + V8DI (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")]) + +(define_mode_iterator AVX512ZEXTMASK + [(DI "TARGET_AVX512BW") (SI "TARGET_AVX512BW") HI]) (define_insn "_testm3" [(set (match_operand: 0 "register_operand" "=Yk") (unspec: - [(match_operand:VI48_AVX512VL 1 "register_operand" "v") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")] + [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v") + (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")] UNSPEC_TESTM))] "TARGET_AVX512F" "vptestm\t{%2, %1, %0|%0, %1, %2}" @@ -12347,25 +12347,74 @@ (define_insn "_testnm3" [(set (match_operand: 0 "register_operand" "=Yk") (unspec: - [(match_operand:VI12_AVX512VL 1 "register_operand" "v") - (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")] - UNSPEC_TESTNM))] - "TARGET_AVX512BW" - "vptestnm\t{%2, %1, %0|%0, %1, %2}" - [(set_attr "prefix" "evex") - (set_attr "mode" "")]) - -(define_insn "_testnm3" - [(set (match_operand: 0 "register_operand" "=Yk") - (unspec: - [(match_operand:VI48_AVX512VL 1 "register_operand" "v") - (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")] + [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v") + (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")] UNSPEC_TESTNM))] "TARGET_AVX512F" "vptestnm\t{%2, %1, %0|%0, %1, %2}" [(set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_insn "*_testm3_zext" + [(set (match_operand:AVX512ZEXTMASK 0 "register_operand" "=Yk") + (zero_extend:AVX512ZEXTMASK + (unspec: + [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v") + (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")] + UNSPEC_TESTM)))] + "TARGET_AVX512BW + && ( + > GET_MODE_SIZE (mode))" + "vptestm\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "*_testm3_zext_mask" + [(set (match_operand:AVX512ZEXTMASK 0 "register_operand" "=Yk") + (zero_extend:AVX512ZEXTMASK + (and: + (unspec: + [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v") + (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")] + UNSPEC_TESTM) + (match_operand: 3 "register_operand" "Yk"))))] + "TARGET_AVX512BW + && ( + > GET_MODE_SIZE (mode))" + "vptestm\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}" + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "*_testnm3_zext" + [(set (match_operand:AVX512ZEXTMASK 0 "register_operand" "=Yk") + (zero_extend:AVX512ZEXTMASK + (unspec: + [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v") + (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")] + UNSPEC_TESTNM)))] + "TARGET_AVX512BW + && ( + > GET_MODE_SIZE (mode))" + "vptestnm\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "*_testnm3_zext_mask" + [(set (match_operand:AVX512ZEXTMASK 0 "register_operand" "=Yk") + (zero_extend:AVX512ZEXTMASK + (and: + (unspec: + [(match_operand:VI1248_AVX512VLBW 1 "register_operand" "v") + (match_operand:VI1248_AVX512VLBW 2 "nonimmediate_operand" "vm")] + UNSPEC_TESTNM) + (match_operand: 3 "register_operand" "Yk"))))] + "TARGET_AVX512BW + && ( + > GET_MODE_SIZE (mode))" + "vptestnm\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}" + [(set_attr "prefix" "evex") + (set_attr "mode" "")]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral element swizzling diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 856dfdf8d45..295b160ee54 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-12-13 Jakub Jelinek + + PR target/88461 + * gcc.target/i386/pr88461.c: New test. + 2018-12-12 Paolo Carlini * g++.dg/other/static5.C: New. diff --git a/gcc/testsuite/gcc.target/i386/pr88461.c b/gcc/testsuite/gcc.target/i386/pr88461.c new file mode 100644 index 00000000000..68349c19710 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr88461.c @@ -0,0 +1,16 @@ +/* PR target/88461 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512vl -mavx512bw" } */ +/* { dg-final { scan-assembler-times "kmovw\[ \t]" 2 } } */ + +#include + +int +foo (const __m128i *data, int a) +{ + __m128i v = _mm_load_si128 (data); + __mmask16 m = _mm_testn_epi16_mask (v, v); + m = _kshiftli_mask16 (m, 1); + m = _kandn_mask16 (m, a); + return m; +}