Hi there,
The "*neon_mov<mode>" patterns for 128 bit sized quantities uses the "Dn" constraint to match vmov.f32 and vmov.i<vec-width> patterns. This constraint boils down to using the `neon_immediate_valid` function. Once the constraint has matched, the output C statement asserts that function passes. The output C statement calls `neon_immediate_valid` with the mode taken from the iterator, while the constraint takes the mode from the operand. This can cause a discrepency when the operand is a CONST_INT, as the constraint passes VOIDmode which `neon_immediate_valid` treats as DImode, while the C statement passes the mode of the iterator which can be TImode. When this happens, the `neon_immediate_valid` can fail in the second call (if e.g. the CONST_INT is a valid immediate in DImode but not TImode) which would trigger the assertion. The testcase added with this patch triggers this when compiled with an arm cross compiler using the command line below. gcc -march=armv8-a -c neon-immediate-timode.c -O1 -mfloat-abi=hard -mfpu=neon-fp-armv8 This patch splits the original "Dn" constraint into three new constraints, "DN" for TImode CONST_INT, "Dn" for DImode CONST_INT, and "Dm" for CONST_VECTOR. Splitting things up this way requires using one extra alternative in the "*neon_mov<mode>" patterns, but makes it clear from the constraint what mode is being used. We also remove the behaviour of treating VOIDmode as DImode in `neon_valid_immediate` since the original "Dn" constraint was the only place that functionality was used. VOIDmode is now never passed to that function. An assertion has been added to the function to ensure this problem is caught earlier on. Bootstrapped on arm-none-linux-gnueabihf Regtested on cross-compiler arm-none-eabi gcc/ChangeLog: 2019-04-09 Matthew Malcomson <matthew.malcomson@arm.com> PR target/90024 * config/arm/arm.c (neon_valid_immediate): Disallow VOIDmode parameter. * config/arm/constraints.md (Dm, DN, Dn): Split previous Dn constraint into three. * config/arm/neon.md (*neon_mov<mode>): Account for TImode and DImode differences directly. (*smax<mode>3_neon, vashl<mode>3, vashr<mode>3_imm): Use Dm constraint. gcc/testsuite/ChangeLog: 2019-04-09 Matthew Malcomson <matthew.malcomson@arm.com> PR target/90024 * gcc.dg/torture/neon-immediate-timode.c: New test. From-SVN: r270226
This commit is contained in:
Matthew Malcomson
Matthew Malcomson
parent
765f8786cf
commit
e009dfb320
@ -1,3 +1,13 @@
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2019-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
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PR target/90024
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* config/arm/arm.c (neon_valid_immediate): Disallow VOIDmode parameter.
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* config/arm/constraints.md (Dm, DN, Dn): Split previous Dn constraint
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into three.
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* config/arm/neon.md (*neon_mov<mode>): Account for TImode and DImode
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differences directly.
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(*smax<mode>3_neon, vashl<mode>3, vashr<mode>3_imm): Use Dm constraint.
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2019-04-09 Jakub Jelinek <jakub@redhat.com>
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PR translation/90011
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@ -11998,8 +11998,7 @@ neon_valid_immediate (rtx op, machine_mode mode, int inverse,
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else
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{
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n_elts = 1;
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if (mode == VOIDmode)
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mode = DImode;
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gcc_assert (mode != VOIDmode);
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}
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innersize = GET_MODE_UNIT_SIZE (mode);
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@ -31,8 +31,8 @@
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;; 'H' was previously used for FPA.
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;; The following multi-letter normal constraints have been used:
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;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, Dl, DL, Do, Dv, Dy, Di, Dt, Dp,
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;; Dz, Tu
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;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di,
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;; Dt, Dp, Dz, Tu
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;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
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;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz
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;; in all states: Pf
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@ -298,14 +298,28 @@
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(and (match_code "const_double,const_int")
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(match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
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(define_constraint "Dn"
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(define_constraint "Dm"
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"@internal
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In ARM/Thumb-2 state a const_vector or const_int which can be loaded with a
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Neon vmov immediate instruction."
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(and (match_code "const_vector,const_int")
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In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
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immediate instruction."
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(and (match_code "const_vector")
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(match_test "TARGET_32BIT
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&& imm_for_neon_mov_operand (op, GET_MODE (op))")))
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(define_constraint "Dn"
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"@internal
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In ARM/Thumb-2 state a DImode const_int which can be loaded with a Neon vmov
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immediate instruction."
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(and (match_code "const_int")
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(match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, DImode)")))
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(define_constraint "DN"
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"@internal
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In ARM/Thumb-2 state a TImode const_int which can be loaded with a Neon vmov
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immediate instruction."
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(and (match_code "const_int")
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(match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, TImode)")))
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(define_constraint "Dl"
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"@internal
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In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
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@ -25,14 +25,14 @@
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(define_insn "*neon_mov<mode>"
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[(set (match_operand:VDX 0 "nonimmediate_operand"
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"=w,Un,w, w, ?r,?w,?r, ?Us,*r")
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"=w,Un,w, w, w, ?r,?w,?r, ?Us,*r")
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(match_operand:VDX 1 "general_operand"
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" w,w, Dn,Uni, w, r, Usi,r,*r"))]
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" w,w, Dm,Dn,Uni, w, r, Usi,r,*r"))]
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"TARGET_NEON
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&& (register_operand (operands[0], <MODE>mode)
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|| register_operand (operands[1], <MODE>mode))"
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{
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if (which_alternative == 2)
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if (which_alternative == 2 || which_alternative == 3)
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{
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int width, is_valid;
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static char templ[40];
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@ -53,32 +53,33 @@
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switch (which_alternative)
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{
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case 0: return "vmov\t%P0, %P1 @ <mode>";
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case 1: case 3: return output_move_neon (operands);
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case 2: gcc_unreachable ();
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case 4: return "vmov\t%Q0, %R0, %P1 @ <mode>";
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case 5: return "vmov\t%P0, %Q1, %R1 @ <mode>";
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case 8: return "#";
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case 1: case 4: return output_move_neon (operands);
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case 2: case 3: gcc_unreachable ();
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case 5: return "vmov\t%Q0, %R0, %P1 @ <mode>";
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case 6: return "vmov\t%P0, %Q1, %R1 @ <mode>";
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case 9: return "#";
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default: return output_move_double (operands, true, NULL);
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}
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}
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[(set_attr "type" "neon_move<q>,neon_store1_1reg,neon_move<q>,\
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neon_load1_1reg, neon_to_gp<q>,neon_from_gp<q>,\
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neon_load1_2reg, neon_store1_2reg, multiple")
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(set_attr "length" "4,4,4,4,4,4,8,8,8")
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(set_attr "arm_pool_range" "*,*,*,1020,*,*,1020,*,*")
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(set_attr "thumb2_pool_range" "*,*,*,1018,*,*,1018,*,*")
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(set_attr "neg_pool_range" "*,*,*,1004,*,*,1004,*,*")])
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neon_move<q>,neon_load1_1reg, neon_to_gp<q>,\
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neon_from_gp<q>,neon_load1_2reg, neon_store1_2reg,\
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multiple")
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(set_attr "length" "4,4,4,4,4,4,4,8,8,8")
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(set_attr "arm_pool_range" "*,*,*,*,1020,*,*,1020,*,*")
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(set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,1018,*,*")
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(set_attr "neg_pool_range" "*,*,*,*,1004,*,*,1004,*,*")])
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(define_insn "*neon_mov<mode>"
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[(set (match_operand:VQXMOV 0 "nonimmediate_operand"
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"=w,Un,w, w, ?r,?w,?r,?r, ?Us")
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"=w,Un,w, w, w, ?r,?w,?r,?r, ?Us")
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(match_operand:VQXMOV 1 "general_operand"
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" w,w, Dn,Uni, w, r, r, Usi, r"))]
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" w,w, Dm,DN,Uni, w, r, r, Usi, r"))]
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"TARGET_NEON
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&& (register_operand (operands[0], <MODE>mode)
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|| register_operand (operands[1], <MODE>mode))"
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{
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if (which_alternative == 2)
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if (which_alternative == 2 || which_alternative == 3)
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{
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int width, is_valid;
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static char templ[40];
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@ -99,20 +100,20 @@
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switch (which_alternative)
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{
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case 0: return "vmov\t%q0, %q1 @ <mode>";
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case 1: case 3: return output_move_neon (operands);
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case 2: gcc_unreachable ();
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case 4: return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1";
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case 5: return "vmov\t%e0, %Q1, %R1 @ <mode>\;vmov\t%f0, %J1, %K1";
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case 1: case 4: return output_move_neon (operands);
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case 2: case 3: gcc_unreachable ();
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case 5: return "vmov\t%Q0, %R0, %e1 @ <mode>\;vmov\t%J0, %K0, %f1";
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case 6: return "vmov\t%e0, %Q1, %R1 @ <mode>\;vmov\t%f0, %J1, %K1";
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default: return output_move_quad (operands);
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}
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}
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[(set_attr "type" "neon_move_q,neon_store2_2reg_q,neon_move_q,\
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neon_load2_2reg_q,neon_to_gp_q,neon_from_gp_q,\
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mov_reg,neon_load1_4reg,neon_store1_4reg")
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(set_attr "length" "4,8,4,8,8,8,16,8,16")
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(set_attr "arm_pool_range" "*,*,*,1020,*,*,*,1020,*")
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(set_attr "thumb2_pool_range" "*,*,*,1018,*,*,*,1018,*")
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(set_attr "neg_pool_range" "*,*,*,996,*,*,*,996,*")])
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neon_move_q,neon_load2_2reg_q,neon_to_gp_q,\
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neon_from_gp_q,mov_reg,neon_load1_4reg,neon_store1_4reg")
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(set_attr "length" "4,8,4,4,8,8,8,16,8,16")
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(set_attr "arm_pool_range" "*,*,*,*,1020,*,*,*,1020,*")
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(set_attr "thumb2_pool_range" "*,*,*,*,1018,*,*,*,1018,*")
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(set_attr "neg_pool_range" "*,*,*,*,996,*,*,*,996,*")])
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/* We define these mov expanders to match the standard mov$a optab to prevent
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the mid-end from trying to do a subreg for these modes which is the most
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@ -1066,7 +1067,7 @@
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(define_insn "vashl<mode>3"
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[(set (match_operand:VDQIW 0 "s_register_operand" "=w,w")
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(ashift:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w,w")
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(match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dn")))]
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(match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Dm")))]
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"TARGET_NEON"
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{
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switch (which_alternative)
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@ -1085,7 +1086,7 @@
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(define_insn "vashr<mode>3_imm"
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[(set (match_operand:VDQIW 0 "s_register_operand" "=w")
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(ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
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(match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dn")))]
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(match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dm")))]
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"TARGET_NEON"
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{
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return neon_output_shift_immediate ("vshr", 's', &operands[2],
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@ -1098,7 +1099,7 @@
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(define_insn "vlshr<mode>3_imm"
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[(set (match_operand:VDQIW 0 "s_register_operand" "=w")
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(lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "w")
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(match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dn")))]
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(match_operand:VDQIW 2 "imm_for_neon_rshift_operand" "Dm")))]
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"TARGET_NEON"
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{
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return neon_output_shift_immediate ("vshr", 'u', &operands[2],
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@ -1,3 +1,8 @@
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2019-04-09 Matthew Malcomson <matthew.malcomson@arm.com>
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PR target/90024
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* gcc.dg/torture/neon-immediate-timode.c: New test.
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2019-04-09 Jakub Jelinek <jakub@redhat.com>
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PR tree-optimization/89998
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10
gcc/testsuite/gcc.dg/torture/neon-immediate-timode.c
Normal file
10
gcc/testsuite/gcc.dg/torture/neon-immediate-timode.c
Normal file
@ -0,0 +1,10 @@
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union a {
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char b;
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long long c;
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};
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union a d;
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int g(int, union a, union a);
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void e() {
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union a f[2] = {-1L};
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g(0, d, f[0]);
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}
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