arm.c: Remove extraneous whitespace.
* config/arm/arm.c: Remove extraneous whitespace. Remove comment describing the deleted arm_gen_rotated_half_load function. From-SVN: r105169
This commit is contained in:
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e0b923193a
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@ -1,3 +1,8 @@
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2005-10-10 Nick Clifton <nickc@redhat.com>
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* config/arm/arm.c: Remove extraneous whitespace. Remove comment
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describing the deleted arm_gen_rotated_half_load function.
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2005-10-09 Kaz Kojima <kkojima@gcc.gnu.org>
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* config/sh/sh.c (emit_fpu_switch): Set TREE_PUBLIC for
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@ -481,7 +481,7 @@ int arm_arch_xscale = 0;
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/* Nonzero if tuning for XScale */
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int arm_tune_xscale = 0;
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/* Nonzero if we want to tune for stores that access the write-buffer.
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/* Nonzero if we want to tune for stores that access the write-buffer.
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This typically means an ARM6 or ARM7 with MMU or MPU. */
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int arm_tune_wbuf = 0;
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@ -867,7 +867,7 @@ arm_override_options (void)
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options. */
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if (i == ARM_OPT_SET_ARCH)
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target_arch_cpu = sel->core;
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if (i != ARM_OPT_SET_TUNE)
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{
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/* If we have been given an architecture and a processor
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@ -1514,7 +1514,7 @@ int
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const_ok_for_arm (HOST_WIDE_INT i)
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{
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int lowbit;
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/* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
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be all zero, or all one. */
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if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
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@ -1524,7 +1524,7 @@ const_ok_for_arm (HOST_WIDE_INT i)
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return FALSE;
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i &= (unsigned HOST_WIDE_INT) 0xffffffff;
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/* Fast return for 0 and small values. We must do this for zero, since
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the code below can't handle that one case. */
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if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
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@ -1766,10 +1766,10 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
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gen_rtx_SET (VOIDmode, target, source));
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return 1;
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}
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/* We don't know how to handle other cases yet. */
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gcc_assert (remainder == 0xffffffff);
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if (generate)
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emit_constant_insn (cond,
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gen_rtx_SET (VOIDmode, target,
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@ -1913,7 +1913,7 @@ arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
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temp1 = 0x80000000 >> (topshift - 1);
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temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
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if (const_ok_for_arm (temp2))
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{
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if (generate)
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@ -2416,11 +2416,11 @@ arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
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mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
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}
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}
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return LIBCALL_VALUE(mode);
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}
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/* Determine the amount of memory needed to store the possible return
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/* Determine the amount of memory needed to store the possible return
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registers of an untyped call. */
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int
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arm_apply_result_size (void)
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@ -2870,10 +2870,10 @@ arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
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attribute. */
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static tree
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arm_handle_notshared_attribute (tree *node,
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tree name ATTRIBUTE_UNUSED,
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tree args ATTRIBUTE_UNUSED,
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int flags ATTRIBUTE_UNUSED,
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arm_handle_notshared_attribute (tree *node,
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tree name ATTRIBUTE_UNUSED,
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tree args ATTRIBUTE_UNUSED,
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int flags ATTRIBUTE_UNUSED,
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bool *no_add_attrs)
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{
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tree decl = TYPE_NAME (*node);
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@ -3189,7 +3189,7 @@ legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
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}
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gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
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base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
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offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
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base == reg ? 0 : reg);
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@ -3266,7 +3266,7 @@ thumb_find_work_register (unsigned long pushed_regs_mask)
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&& current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
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&& cfun->args_info.nregs < 4)
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return LAST_ARG_REGNUM;
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/* Otherwise look for a call-saved register that is going to be pushed. */
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for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
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if (pushed_regs_mask & (1 << reg))
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@ -3866,13 +3866,13 @@ thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
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}
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rtx
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thumb_legitimize_reload_address(rtx *x_p,
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enum machine_mode mode,
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int opnum, int type,
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int ind_levels ATTRIBUTE_UNUSED)
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thumb_legitimize_reload_address (rtx *x_p,
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enum machine_mode mode,
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int opnum, int type,
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int ind_levels ATTRIBUTE_UNUSED)
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{
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rtx x = *x_p;
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if (GET_CODE (x) == PLUS
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&& GET_MODE_SIZE (mode) < 4
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&& REG_P (XEXP (x, 0))
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@ -3907,9 +3907,7 @@ thumb_legitimize_reload_address(rtx *x_p,
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return NULL;
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}
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#define REG_OR_SUBREG_REG(X) \
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(GET_CODE (X) == REG \
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|| (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
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@ -6114,10 +6112,6 @@ arm_gen_movmemqi (rtx *operands)
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return 1;
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}
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/* Generate a memory reference for a half word, such that it will be loaded
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into the top 16 bits of the word. We can assume that the address is
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known to be alignable and of the form reg, or plus (reg, const). */
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/* Select a dominance comparison mode if possible for a test of the general
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form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
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COND_OR == DOM_CC_X_AND_Y => (X && Y)
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case LT:
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if (cond_or == DOM_CC_X_AND_Y)
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return CC_DLTmode;
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switch (cond2)
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{
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case LT:
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@ -6229,7 +6223,7 @@ arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
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case GTU:
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if (cond_or == DOM_CC_X_AND_Y)
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return CC_DGTUmode;
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switch (cond2)
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{
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case GTU:
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@ -6749,7 +6743,6 @@ arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
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return !BYTES_BIG_ENDIAN;
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}
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/* Print a symbolic form of X to the debug file, F. */
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static void
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@ -7656,17 +7649,17 @@ arm_const_double_inline_cost (rtx val)
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{
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rtx lowpart, highpart;
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enum machine_mode mode;
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mode = GET_MODE (val);
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if (mode == VOIDmode)
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mode = DImode;
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gcc_assert (GET_MODE_SIZE (mode) == 8);
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lowpart = gen_lowpart (SImode, val);
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highpart = gen_highpart_mode (SImode, mode, val);
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gcc_assert (GET_CODE (lowpart) == CONST_INT);
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gcc_assert (GET_CODE (highpart) == CONST_INT);
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@ -7691,23 +7684,23 @@ arm_const_double_by_parts (rtx val)
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if (mode == VOIDmode)
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mode = DImode;
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part = gen_highpart_mode (SImode, mode, val);
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gcc_assert (GET_CODE (part) == CONST_INT);
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if (const_ok_for_arm (INTVAL (part))
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|| const_ok_for_arm (~INTVAL (part)))
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return true;
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part = gen_lowpart (SImode, val);
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gcc_assert (GET_CODE (part) == CONST_INT);
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if (const_ok_for_arm (INTVAL (part))
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|| const_ok_for_arm (~INTVAL (part)))
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return true;
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return false;
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}
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case REG:
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output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
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break;
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case PRE_INC:
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gcc_assert (TARGET_LDRD);
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output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
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break;
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case PRE_DEC:
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output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
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break;
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case POST_INC:
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output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
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break;
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case POST_DEC:
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gcc_assert (TARGET_LDRD);
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output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
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break;
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case PRE_MODIFY:
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case POST_MODIFY:
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otherops[0] = operands[0];
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otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
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otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
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if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
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{
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if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
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output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
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}
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break;
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case LABEL_REF:
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case CONST:
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output_asm_insn ("adr%?\t%0, %1", operands);
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output_asm_insn ("ldm%?ia\t%0, %M0", operands);
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break;
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default:
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if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
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GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
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otherops[0] = operands[0];
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otherops[1] = XEXP (XEXP (operands[1], 0), 0);
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otherops[2] = XEXP (XEXP (operands[1], 0), 1);
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if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
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{
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if (GET_CODE (otherops[2]) == CONST_INT)
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avoid a conflict. */
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otherops[1] = XEXP (XEXP (operands[1], 0), 1);
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otherops[2] = XEXP (XEXP (operands[1], 0), 0);
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}
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/* If both registers conflict, it will usually
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have been fixed by a splitter. */
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output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops);
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return "";
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}
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if (GET_CODE (otherops[2]) == CONST_INT)
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{
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if (!(const_ok_for_arm (INTVAL (otherops[2]))))
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@ -8865,7 +8857,7 @@ arm_compute_save_reg0_reg12_mask (void)
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/* If we aren't loading the PIC register,
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don't stack it even though it may be live. */
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if (flag_pic
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&& !TARGET_SINGLE_PIC_BASE
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&& !TARGET_SINGLE_PIC_BASE
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&& (regs_ever_live[PIC_OFFSET_TABLE_REGNUM]
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|| current_function_uses_pic_offset_table))
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save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
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else
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{
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gcc_assert (seeking_return || arm_ccfsm_state == 2);
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while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
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{
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this_insn = next_nonnote_insn (this_insn);
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if (frame_pointer_needed)
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{
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amount = offsets->outgoing_args - offsets->locals_base;
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if (amount < 1024)
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insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
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stack_pointer_rtx, GEN_INT (amount)));
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emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
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amount = offsets->locals_base - offsets->saved_regs;
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}
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if (amount)
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{
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if (amount < 512)
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@ -13697,7 +13689,7 @@ thumb_load_double_from_address (rtx *operands)
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{
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case REG:
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operands[2] = adjust_address (operands[1], SImode, 4);
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if (REGNO (operands[0]) == REGNO (addr))
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{
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output_asm_insn ("ldr\t%H0, %2", operands);
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@ -13713,7 +13705,7 @@ thumb_load_double_from_address (rtx *operands)
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case CONST:
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/* Compute <address> + 4 for the high order load. */
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operands[2] = adjust_address (operands[1], SImode, 4);
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output_asm_insn ("ldr\t%0, %1", operands);
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output_asm_insn ("ldr\t%H0, %2", operands);
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break;
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@ -13755,7 +13747,6 @@ thumb_load_double_from_address (rtx *operands)
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{
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/* Compute <address> + 4 for the high order load. */
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operands[2] = adjust_address (operands[1], SImode, 4);
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/* If the computed address is held in the low order register
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then load the high order register first, otherwise always
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@ -14616,7 +14607,7 @@ arm_cxx_determine_class_data_visibility (tree decl)
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DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
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DECL_VISIBILITY_SPECIFIED (decl) = 1;
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}
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static bool
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arm_cxx_class_data_always_comdat (void)
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{
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@ -14851,11 +14842,11 @@ arm_unwind_emit_stm (FILE * asm_out_file, rtx p)
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|| GET_CODE (XEXP (e, 0)) != MEM
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|| GET_CODE (XEXP (e, 1)) != REG)
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abort ();
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reg = REGNO (XEXP (e, 1));
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if (reg < lastreg)
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abort ();
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if (i != 1)
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fprintf (asm_out_file, ", ");
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/* We can't use %r for vfp because we need to use the
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@ -14930,7 +14921,7 @@ arm_unwind_emit_set (FILE * asm_out_file, rtx p)
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{
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HOST_WIDE_INT offset;
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unsigned reg;
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if (GET_CODE (e1) == PLUS)
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{
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if (GET_CODE (XEXP (e1, 0)) != REG
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