Ian Lance Taylor
parent
8926095fe7
commit
e0bfcea5c9
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@ -3191,6 +3191,28 @@ override_options ()
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else
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mips_abicalls = MIPS_ABICALLS_NO;
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/* -membedded-pic is a form of PIC code suitable for embedded
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systems. All calls are made using PC relative addressing, and
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all data is addressed using the $gp register. This requires gas,
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which does most of the work, and GNU ld, which automatically
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expands PC relative calls which are out of range into a longer
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instruction sequence. All gcc really does differently is
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generate a different sequence for a switch. */
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if (TARGET_EMBEDDED_PIC)
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{
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flag_pic = 1;
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if (TARGET_ABICALLS)
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warning ("-membedded-pic and -mabicalls are incompatible");
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if (g_switch_set)
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warning ("-G and -membedded-pic are incompatible");
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/* Setting mips_section_threshold is not required, because gas
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will force everything to be GP addressable anyhow, but
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setting it will cause gcc to make better estimates of the
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number of instructions required to access a particular data
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item. */
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mips_section_threshold = 0x7fffffff;
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}
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/* -mrnames says to use the MIPS software convention for register
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names instead of the hardware names (ie, $a0 instead of $4).
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We do this by switching the names in mips_reg_names, which the
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@ -3387,6 +3409,7 @@ mips_debugger_offset (addr, offset)
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'M' print high-order register of double-word register operand.
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'C' print part of opcode for a branch condition.
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'N' print part of opcode for a branch condition, inverted.
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'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
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'(' Turn on .set noreorder
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')' Turn on .set reorder
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'[' Turn on .set noat
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@ -3569,6 +3592,14 @@ print_operand (file, op, letter)
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abort_with_insn (op, "PRINT_OPERAND, illegal insn for %%N");
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}
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else if (letter == 'S')
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{
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char buffer[100];
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ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
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assemble_name (file, buffer);
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}
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else if (code == REG)
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{
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register int regnum = REGNO (op);
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@ -254,12 +254,12 @@ extern char *mktemp ();
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#define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
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#define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
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#define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
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#define MASK_UNUSED1 0x00004000
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#define MASK_UNUSED2 0x00008000
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#define MASK_UNUSED3 0x00010000
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#define MASK_UNUSED4 0x00020000
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#define MASK_UNUSED5 0x00040000
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#define MASK_UNUSED6 0x00080000
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#define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
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#define MASK_UNUSED1 0x00008000
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#define MASK_UNUSED2 0x00010000
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#define MASK_UNUSED3 0x00020000
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#define MASK_UNUSED4 0x00040000
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#define MASK_UNUSED5 0x00080000
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/* Dummy switches used only in spec's*/
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#define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
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@ -327,6 +327,10 @@ extern char *mktemp ();
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/* always call through a register */
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#define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
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/* generate embedded PIC code;
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requires gas. */
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#define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
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/* Macro to define tables used to set the flags.
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This is a list in braces of pairs in braces,
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each pair being { "NAME", VALUE }
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@ -364,6 +368,8 @@ extern char *mktemp ();
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{"no-half-pic", -MASK_HALF_PIC}, \
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{"long-calls", MASK_LONG_CALLS}, \
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{"no-long-calls", -MASK_LONG_CALLS}, \
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{"embedded-pic", MASK_EMBEDDED_PIC}, \
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{"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
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{"debug", MASK_DEBUG}, \
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{"debuga", MASK_DEBUG_A}, \
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{"debugb", MASK_DEBUG_B}, \
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@ -552,7 +558,8 @@ while (0)
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%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
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%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
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%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
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%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
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%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
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%{membedded-pic}"
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#else
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/* not GAS */
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@ -568,7 +575,8 @@ while (0)
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%{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
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%{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
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%{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
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%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
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%{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
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%{membedded-pic}"
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#endif
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#endif /* ASM_SPEC */
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@ -3375,12 +3383,33 @@ do { \
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VALUE)
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/* This is how to output an element of a case-vector that is relative.
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This is used for pc-relative code (e.g. when TARGET_ABICALLS). */
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This is used for pc-relative code (e.g. when TARGET_ABICALLS or
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TARGET_EMBEDDED_PIC). */
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#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, VALUE, REL) \
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fprintf (STREAM, "\t%s\t$L%d\n", \
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TARGET_LONG64 ? ".gpdword" : ".gpword", \
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VALUE)
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do { \
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if (TARGET_EMBEDDED_PIC) \
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fprintf (STREAM, "\t%s\t$L%d-$LS%d\n", \
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TARGET_LONG64 ? ".dword" : ".word", \
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VALUE, REL); \
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else \
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fprintf (STREAM, "\t%s\t$L%d\n", \
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TARGET_LONG64 ? ".gpdword" : ".gpword", \
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VALUE); \
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} while (0)
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/* When generating embedded PIC code we want to put the jump table in
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the .text section. In all other cases, we want to put the jump
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table in the .rdata section. Unfortunately, we can't use
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JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
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Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
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section if appropriate. */
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#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
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do { \
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if (TARGET_EMBEDDED_PIC) \
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text_section (); \
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ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
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} while (0)
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/* This is how to output an assembler line
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that says to advance the location counter
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@ -5410,6 +5410,90 @@ move\\t%0,%z4\\n\\
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(set_attr "mode" "none")
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(set_attr "length" "1")])
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;; Implement a switch statement when generating embedded PIC code.
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;; Switches are implemented by `tablejump' when not using -membedded-pic.
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(define_expand "casesi"
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[(set (match_dup 5)
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(minus:SI (match_operand:SI 0 "register_operand" "d")
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(match_operand:SI 1 "arith_operand" "dI")))
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(set (cc0)
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(compare:CC (match_dup 5)
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(match_operand:SI 2 "arith_operand" "")))
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(set (pc)
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(if_then_else (gtu (cc0)
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(const_int 0))
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(label_ref (match_operand 4 "" ""))
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(pc)))
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(parallel
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[(set (pc)
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(mem:SI (plus:SI (mult:SI (match_dup 5)
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(const_int 4))
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(label_ref (match_operand 3 "" "")))))
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(clobber (match_scratch:SI 6 ""))
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(clobber (reg:SI 31))])]
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"TARGET_EMBEDDED_PIC"
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"
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{
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/* We need slightly different code for eight byte table entries. */
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if (TARGET_LONG64)
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abort ();
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if (operands[0])
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{
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rtx reg = gen_reg_rtx (SImode);
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/* The constraints should handle this, but they don't. */
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operands[0] = force_reg (SImode, operands[0]);
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if (! arith_operand (operands[1]))
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operands[1] = force_reg (SImode, operands[1]);
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if (! arith_operand (operands[2]))
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operands[2] = force_reg (SImode, operands[2]);
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/* If the index is too large, go to the default label. */
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emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
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emit_insn (gen_cmpsi (reg, operands[2]));
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emit_insn (gen_bgtu (operands[4]));
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/* Do the PIC jump. */
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emit_insn (gen_casesi_internal (reg, operands[3], gen_reg_rtx (SImode)));
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DONE;
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}
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}")
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;; An embedded PIC switch statement looks like this:
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;; bal $LS1
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;; sll $reg,$index,2
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;; $LS1:
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;; addu $reg,$reg,$31
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;; lw $reg,$L1-$LS1($reg)
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;; addu $reg,$reg,$31
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;; j $reg
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;; $L1:
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;; .word case1-$LS1
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;; .word case2-$LS1
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;; ...
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(define_insn "casesi_internal"
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[(set (pc)
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(mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d")
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(const_int 4))
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(label_ref (match_operand 1 "" "")))))
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(clobber (match_operand:SI 2 "register_operand" "d"))
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(clobber (reg:SI 31))]
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"TARGET_EMBEDDED_PIC"
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"*
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{
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output_asm_insn (\"%(bal\\t%S1\;sll\\t%0,2\\n%S1:\", operands);
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output_asm_insn (\"addu\\t%0,%0,$31%)\", operands);
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output_asm_insn (\"lw\\t%0,%1-%S1(%0)\;addu\\t%0,%0,$31\", operands);
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return \"j\\t%0\";
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}"
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[(set_attr "type" "jump")
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(set_attr "mode" "none")
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(set_attr "length" "6")])
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;;
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;; ....................
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