Delete incorrect representations of avx2 shifts.
* config/i386/i386.c (bdesc_args): Update code for __builtin_ia32_palignr256. Change type of __builtin_ia32_pslldqi256, and __builtin_ia32_psrldqi256 to V4DI_FTYPE_V4DI_INT_CONVERT. (ix86_expand_args_builtin): Handle V4DI_FTYPE_V4DI_INT_CONVERT. * config/i386/sse.md (mode iterator V16): Add V2TI. (mode iterator SSESCALARMODE): Use V2TI not V4DI. (mode attr ssse3_avx2): Add V2TI. (avx2_lshrqv4di3, avx2_lshlqv4di3): Remove. From-SVN: r179668
This commit is contained in:
Richard Henderson
Richard Henderson
parent
26e2f443df
commit
e1faf1503e
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@ -1,3 +1,14 @@
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2011-10-07 Richard Henderson <rth@redhat.com>
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* config/i386/i386.c (bdesc_args): Update code for
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__builtin_ia32_palignr256. Change type of __builtin_ia32_pslldqi256,
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and __builtin_ia32_psrldqi256 to V4DI_FTYPE_V4DI_INT_CONVERT.
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(ix86_expand_args_builtin): Handle V4DI_FTYPE_V4DI_INT_CONVERT.
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* config/i386/sse.md (mode iterator V16): Add V2TI.
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(mode iterator SSESCALARMODE): Use V2TI not V4DI.
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(mode attr ssse3_avx2): Add V2TI.
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(avx2_lshrqv4di3, avx2_lshlqv4di3): Remove.
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2011-10-07 David S. Miller <davem@davemloft.net>
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PR 50655
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@ -26107,7 +26107,7 @@ static const struct builtin_description bdesc_args[] =
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv4di, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
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@ -26171,7 +26171,7 @@ static const struct builtin_description bdesc_args[] =
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshlqv4di3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
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@ -26182,7 +26182,7 @@ static const struct builtin_description bdesc_args[] =
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrqv4di3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
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{ OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
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@ -27812,6 +27812,11 @@ ix86_expand_args_builtin (const struct builtin_description *d,
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rmode = V1TImode;
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nargs_constant = 1;
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break;
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case V4DI_FTYPE_V4DI_INT_CONVERT:
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nargs = 2;
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rmode = V2TImode;
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nargs_constant = 1;
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break;
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case V8HI_FTYPE_V8HI_INT:
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case V8HI_FTYPE_V8SF_INT:
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case V8HI_FTYPE_V4SF_INT:
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@ -18,13 +18,13 @@
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; All vector modes including V1TImode, used in move patterns.
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;; All vector modes including V?TImode, used in move patterns.
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(define_mode_iterator V16
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[(V32QI "TARGET_AVX") V16QI
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(V16HI "TARGET_AVX") V8HI
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(V8SI "TARGET_AVX") V4SI
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(V4DI "TARGET_AVX") V2DI
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V1TI
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(V2TI "TARGET_AVX") V1TI
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(V8SF "TARGET_AVX") V4SF
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(V4DF "TARGET_AVX") V2DF])
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@ -99,11 +99,13 @@
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(define_mode_iterator VI8_AVX2
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[(V4DI "TARGET_AVX2") V2DI])
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;; ??? We should probably use TImode instead.
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(define_mode_iterator VIMAX_AVX2
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[(V2TI "TARGET_AVX2") V1TI])
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;; ??? This should probably be dropped in favor of VIMAX_AVX2.
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(define_mode_iterator SSESCALARMODE
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[(V4DI "TARGET_AVX2") TI])
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[(V2TI "TARGET_AVX2") TI])
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(define_mode_iterator VI12_AVX2
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[(V32QI "TARGET_AVX2") V16QI
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@ -147,7 +149,7 @@
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(V8HI "ssse3") (V16HI "avx2")
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(V4SI "ssse3") (V8SI "avx2")
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(V2DI "ssse3") (V4DI "avx2")
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(TI "ssse3")])
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(TI "ssse3") (V2TI "avx2")])
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(define_mode_attr sse4_1_avx2
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[(V16QI "sse4_1") (V32QI "avx2")
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@ -5649,21 +5651,6 @@
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "avx2_lshrqv4di3"
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[(set (match_operand:V4DI 0 "register_operand" "=x")
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(lshiftrt:V4DI
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(match_operand:V4DI 1 "register_operand" "x")
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(match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
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"TARGET_AVX2"
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{
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operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
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return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
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}
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[(set_attr "type" "sseishft")
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(set_attr "prefix" "vex")
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(set_attr "length_immediate" "1")
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(set_attr "mode" "OI")])
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(define_insn "lshr<mode>3"
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[(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x")
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(lshiftrt:VI248_AVX2
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@ -5683,20 +5670,6 @@
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn "avx2_lshlqv4di3"
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[(set (match_operand:V4DI 0 "register_operand" "=x")
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(ashift:V4DI (match_operand:V4DI 1 "register_operand" "x")
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(match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
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"TARGET_AVX2"
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{
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operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
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return "vpslldq\t{%2, %1, %0|%0, %1, %2}";
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}
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[(set_attr "type" "sseishft")
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(set_attr "prefix" "vex")
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(set_attr "length_immediate" "1")
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(set_attr "mode" "OI")])
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(define_insn "avx2_lshl<mode>3"
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[(set (match_operand:VI248_256 0 "register_operand" "=x")
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(ashift:VI248_256
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