OpenE2K
/
gcc
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

alpha.md (one_cmpl<mode>2, [...]): New macroized vector operate patterns. 

* config/alpha/alpha.md (one_cmpl<mode>2, and<mode>3, andnot<mode>3,
        ior<mode>3, iornot<mode>3, xor<mode>3, xornot<mode>3): New macroized
        vector operate patterns.

From-SVN: r92545
This commit is contained in:
Richard Henderson 2004-12-23 02:32:42 -08:00 committed by Richard Henderson
parent 3e8aba3481
commit e26b63b29f
2 changed files with 61 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2004-12-23 Richard Henderson <rth@redhat.com>
* config/alpha/alpha.md (one_cmpl<mode>2, and<mode>3, andnot<mode>3,
ior<mode>3, iornot<mode>3, xor<mode>3, xornot<mode>3): New macroized
vector operate patterns.
2004-12-23 Richard Henderson <rth@redhat.com>
* config/i386/i386.c (ix86_expand_vector_move): Tidy.

55
gcc/config/alpha/alpha.md
View File

@ -6207,6 +6207,61 @@
"TARGET_MAX"
"maxsw4 %r1,%r2,%0"
[(set_attr "type" "mvi")])
(define_insn "one_cmpl<mode>2"
[(set (match_operand:VEC 0 "register_operand" "=r")
(not:VEC (match_operand:VEC 1 "register_operand" "r")))]
""
"ornot $31,%1,%0"
[(set_attr "type" "ilog")])
(define_insn "and<mode>3"
[(set (match_operand:VEC 0 "register_operand" "=r")
(and:VEC (match_operand:VEC 1 "register_operand" "r")
(match_operand:VEC 2 "register_operand" "r")))]
""
"and %1,%2,%0"
[(set_attr "type" "ilog")])
(define_insn "*andnot<mode>3"
[(set (match_operand:VEC 0 "register_operand" "=r")
(and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
(match_operand:VEC 2 "register_operand" "r")))]
""
"bic %2,%1,%0"
[(set_attr "type" "ilog")])
(define_insn "ior<mode>3"
[(set (match_operand:VEC 0 "register_operand" "=r")
(ior:VEC (match_operand:VEC 1 "register_operand" "r")
(match_operand:VEC 2 "register_operand" "r")))]
""
"bis %1,%2,%0"
[(set_attr "type" "ilog")])
(define_insn "*iornot<mode>3"
[(set (match_operand:VEC 0 "register_operand" "=r")
(ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
(match_operand:VEC 2 "register_operand" "r")))]
""
"ornot %2,%1,%0"
[(set_attr "type" "ilog")])
(define_insn "xor<mode>3"
[(set (match_operand:VEC 0 "register_operand" "=r")
(xor:VEC (match_operand:VEC 1 "register_operand" "r")
(match_operand:VEC 2 "register_operand" "r")))]
""
"xor %1,%2,%0"
[(set_attr "type" "ilog")])
(define_insn "*xornot<mode>3"
[(set (match_operand:VEC 0 "register_operand" "=r")
(not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
(match_operand:VEC 2 "register_operand" "r"))))]
""
"eqv %1,%2,%0"
[(set_attr "type" "ilog")])
;; Bit field extract patterns which use ext[wlq][lh]